Simulate with the Aldec Active HDL or Riviera-PRO Simulator

By default, the Efinity® software calls the iVerilog simulator. Use the --aldec option to target the Active HDL or Riviera-PRO simulators instead.

Note: The simulator must be in your path for the simulation to run properly.

For example, the commands to simulate are:

Simulate with Aldec Active HDL or Riviera-PRO

Linux:

efx_run.py <project name>.xml --flow rtlsim --aldec     // Behavioral simulation
efx_run.py <project name>.xml --flow map                // Synthesize the design
efx_run.py <project name>.xml --flow mapsim --aldec     // Post-synthesis simulation

Windows:

efx_run.bat <project name>.xml --flow rtlsim --aldec     // Behavioral simulation
efx_run.bat <project name>.xml --flow map                // Synthesize the design
efx_run.bat <project name>.xml --flow mapsim --aldec     // Post-synthesis simulation

Note: The Aldec Active HDL simulator can be used in GUI mode with the

--sim_opts
                    gui

option.

Linux:

efx_run.py <project name>.xml --flow rtlsim --aldec --sim_opts gui

Windows:

efx_run.bat <project name>.xml --flow rtlsim --aldec --sim_opts gui

The simulator responds with

PASS if the simulation is successful.
FAIL if the simulation is unsuccessful.

The software saves simulation results (<flow>.rtl.simlog and <flow>.map.simlog) and error messages (<flow>.log) in your project's outflow directory.