Using the create_clock Constraint

Any interface block that can be a clock source (PLL, GPIOs, MIPI RX Lane, MIPI RX/TX PHY, and JTAG) has an auto-generated create_clock constraint in the <project>.pt.sdc. There are several cases:

Constraints where the software knows the clock value. <project>.pt.sdc includes the number.
Constraints where you have to define the clock value (typically, GPIO resources being used as GCLK, RCLK, and JTAG TCK). These constraints are commented out and have a placeholder for you to add in the number.

A GPIO with a connection type other than GCLK, RCLK, or JTAG TCK does not have a template (because the software thinks they are not clocks). You need to write your own create_clock command.

Tip: Common mistakes when using create_clock SDC command:

Using the -name option without a target (e.g., get_ports) and thereby creating a virtual clock by mistake. The Efinity software prints an info message when it finds a virtual clock definition.

Using the instance name instead of the clock pin name. The clock pin name you use in the Interface Designer is the name used in the core timing netlist.

Example: PLL

The PLL Timing Report section shows the details about the clock generated by PLLs in the interface. Details including clock period, phase shift, and whether the clock is inverted are listed in the section. You copy the constraints from <project>.pt.sdc into your SDC file, you do not need to change them.

# PLL Constraints
#################
create_clock -period 10.0000 i_hbramClk_fb
create_clock -waveform {1.2500 3.7500} -period 5.0000 i_hbramClk90
...

Example: GPIO Clock (GCLK and RCLK)

The following sections have create_clock constraint templates that you need to modify:

GPIO Constraints
HSIO GPIO Constraints (Titanium and Topaz only)

To constrain these clocks, replace <USER_PERIOD> in the create_clock template line with the clock period and uncomment the line. If necessary, you can define the waveform if the clock is not using a standard 50/50 duty cycle.

Template

# GPIO Constraints
####################
# create_clock -period <USER_PERIOD> [get_ports {clock}]
...

Your SDC File

create_clock -period 10 [get_ports {clock}]

Example: Regular GPIO Used as a Clock

You need to use a regular GPIO as a clock, for example if you need a bidirectional signal that sometimes acts as a clock. In this case you need to write your own create_clock command because the software cannot generate a template for it.

Note: If the Efinity software detects a signal that it thinks is a clock but you have not specified the GPIO as a GCLK or RCLK, the software gives a warning.

Important: Efinix does not recommend using a regular GPIO as a clock for Trion FPGAs because it will have to route to the global clock network (GCLK), which results in additional and variable delay.

For simple inputs and outputs, the instance name and pin name are usually the same (just to make things easier). A GPIO in inout mode has three pins with different names. The following example has instance bclk with 3 pin names for the input, output, and output enable.

Timing Report for GPIO in inout Mode

---------- 1.1 HSIO GPIO Timing Report (begin) ----------
 
Non-registered HSIO GPIO Configuration:
========================================
 
+---------------+----------+-----------+----------+----------+
| Instance Name | Pin Name | Parameter | Max (ns) | Min (ns) |
+---------------+----------+-----------+----------+----------+
|      bclk     | bclk_IN  |  GPIO_IN  |  0.828   |  0.552   |
|      bclk     | bclk_OUT |  GPIO_OUT |  2.205   |  1.470   |
|      bclk     | bclk_OE  |  GPIO_OUT |  1.953   |  1.302   |
+---------------+----------+-----------+----------+----------+
 
---------- HSIO GPIO Timing Report (end) ----------

For this case, the create_clock constraint is:

create_clock -period 10 -name bclk [get_ports bclk_IN]

Note: The constraint does not use bclk for get_ports, it uses the pin name not the instance.