Supported IP Cores by Family
Not all IP cores work with all Titanium or Trion FPGAs. For example, IP cores that connect to DDR DRAM memory will not work with FPGA that does not have a hard DDR DRAM interface. The following table shows which IP is supported in which FPGA.
Note: Refer to the FPGA Selector Guide for more
information about supported blocks in each FPGA package.
| IP Core | Trion | Titanium | Topaz | |||
|---|---|---|---|---|---|---|
| Supported | Not Supported | Supported | Not Supported | Supported | Not Supported | |
| AXI Infrastructures | ||||||
|
AXI Data FIFO
|
All | All | All | |||
|
AXI Interconnect
|
All | All | All | |||
|
AXI4-Stream Switch
|
All | All | All | |||
| Arithmetic | ||||||
|
CORDIC
|
All | All | All | |||
|
Divider
|
All | All | All | |||
|
Integer Square Root
|
All | All | All | |||
| Bridges and Adaptors | ||||||
|
ABP Interconnect
|
All | All | All | |||
|
APB3 to AXI4 Lite Converter
|
All | All | All | |||
|
Data Pipeline
|
All | All | All | |||
|
Direct Memory Access
|
All | All | All | |||
|
PCIe Scatter-Gather Direct Memory Access
|
Ti85, Ti135, Ti165, Ti240, and Ti375 | All others | Tz75, Tz100, Tz200, Tz325 | All others | ||
| Ethernet | ||||||
|
Triple Speed Ethernet MAC
|
All | All | All | |||
|
10G Ethernet MAC
|
All | Ti85, Ti135, Ti165, Ti240, Ti375 | All others | Tz75, Tz100, Tz200, Tz325 | All others | |
|
USXGMII Multirate Ethernet Core
|
All | Ti85, Ti135, Ti165, Ti240, Ti375 | All others | Tz75, Tz100, Tz200, Tz325 | All others | |
| Foundation IP | ||||||
|
PLL Dynamic Reconfiguration
|
All | Ti85, Ti135, Ti165, Ti240, Ti375 | All others | Tz75, Tz100, Tz200, Tz325 | All others | |
|
Trion PLL Auto-Reset
|
All others | T4F49, T4F81, T8F49, T8F81 | All | All | ||
| Memory | ||||||
|
BRAM Wrapper
|
All | All | All | |||
|
FIFO
|
All | All | All | |||
| Memory Controllers | ||||||
|
ASMI SPI Flash Controller
|
All | All | All | |||
|
DDR Hard Memory Controller-Reset
|
T20, T35, T55, T85, T120 | T4, T8, T13 | All | All | ||
|
DDR3 Soft Controller
|
All | All | All | |||
|
HyperRAM Controller
|
All | All | All | |||
|
JTAG to SPI Flash
|
All | All | All | |||
|
SDRAM Controller
|
All | All | All | |||
|
SD Host Controller
|
All | All | All | |||
|
Trion DDR Calibration and
Debug
|
T20 (BGA324 and BGA400 only), T35, T55, T85, T120 FPGAs | T4, T8, T13 | All | All | ||
| MIPI | ||||||
|
MIPI 2.5G CSI-2 RX Controller
MIPI 2.5G CSI-2 TX Controller
|
All | Ti90, Ti120, Ti180 | Ti35, Ti60 | Tz110, Tz170 | Tz50 | |
|
MIPI D-PHY BIDIR RX Controller
MIPI D-PHY BIDIR TX Controller
|
All | All | All | |||
|
MIPI CSI-2 RX Controller
MIPI CSI-2 TX Controller
|
All | All | All | |||
|
MIPI D-PHY RX Controller
MIPI D-PHY TX Controller
|
All | All | All | |||
|
MIPI DSI RX Controller
MIPI DSI TX Controller
|
All | All | All | |||
| Processors and Peripherals | ||||||
|
Sapphire SoC
|
All except T4 | T4 | All | |||
|
Sapphire High-Performance SoC
|
Ti165, Ti240, Ti375 | Tz200, Tz325 | ||||
| Serial Interface Protocols | ||||||
|
I2C
|
All | All | All | |||
|
UART
|
All | All | All | |||
|
JTAG
|
All | All | All | |||
| IP Core | End of Life in Version | Replaced By | Trion | Titanium | ||
|---|---|---|---|---|---|---|
| Supported | Not Supported | Supported | Not Supported | |||
| JTAG SPI Flash Loader | 2025.1 | JTAG Bridge | All | All | ||
| Jade SoC | 2022.1 | Sapphire SoC | T8, T13, T20, T35, T55, T85, T120 | T4 | All | |
| Opal SoC | 2022.1 | Sapphire SoC | All except T4 | T4 | All | |
| Ruby SoC | 2022.1 | Sapphire SoC | T35, T55, T85, T120 | T4, T8, T13, T20 | All | |
| DDR Hard Memory Controller-Calibration | 2022.1 | DDR Hard Memory Controller-Calibration and Reset | T20, T35, T55, T85, T120 | T4, T8, T13 | All | |
| DDR Hard Memory Controller-Calibration and Reset | 2024.2 | Trion DDR Calibration and Debug | T20, T35, T55, T85, T120 | T4, T8, T13 | All | |
| FIFO (Legacy) | 2021.1 | FIFO | All | All | ||