PLL Property Reference

Efinix FPGAs have seveal types of PLLs to provide clock sources.

Table 1. PLL Types by Family
PLL Type Family Reference
Simple PLL Trion PLL_V1
Advanced PLL Trion PLL_V2
Full featured PLL Titanium and Topaz PLL_V3
Fractional PLL Titanium and Topaz FPLL_V1
Table 2. PLL PropertiesTrion FPGAs: n is 0, 1, or 2
Titanium and Topaz FPGAs: n is 0, 1, 2, 3, or 4
API Name GUI Name PLL_V1 PLL_V2 PLL_V3 FPLL_V1 Values
CFG_CLK_PIN Configuration Clock Pin Name Pin name
CFG_DATA_IN_PIN Configuration Data Input Pin Name Pin name
CFG_DATA_OUT_PIN Configuration Data Output Pin Name Pin name
CFG_SEL_PIN Configuration Select Pin Name Pin name
CLKOUTn_EN Enable Output Clock n 0, 1
CLKOUTn_DIV Output Clock n Divider 2, 4, 8, 16, 32, 64, 128, 256
1 - 256
1 - 128
CLKOUTn_FREQ Output Clock n Frequency Calculated value in MHz
CLKOUTn_INVERT_EN Output Clock n Enable Invert Enable inversion
CLKOUTn_PIN Output Clock n Pin Name Pin name
CLKOUTn_PHASE Phase Shift (Degree) 0, 45, 90, 135, 180, 270
Calculated phase shift
CLKOUTn_DYNPHASE_EN Output Clock n Enable Dynamic Phase 0, 1
CLKOUTn_PHASE_SETTING
CLKOUTn_PHASE_STEP1
 Output Clock n Phase Shift Setting 0 - 7
CLKOUTn_CONN_TYPE Output Clock n Connection Type2
 GCLK, RCLK
CLKOUTn_CLKMUX_BUF_PIN Output Clock n Buffered Pin Name2 Pin name
CORE_CLK_PIN
CORE_CLK1_PIN
 Clock Source - Dynamic Clock - Core Clock [0 |1] Name Clock name
CLKOUT1_PROG_DUTY_CYCLE_EN Output Clock 1 Programmable Duty Cycle 0, 1
CLKOUT1_REQUEST_DUTY_CYCLE Output Clock 1 Request Duty Cycle 0 - 99
CLKOUT1_SDIV Output Clock 1 S Divider 1 - 64
CLKOUT1_PDIV Output Clock 1 P Divider 1 - 64
CLKOUT1_DUTY_CYCLE Output Clock 1 Actual Duty Cycle 0 - 99
CLKOUT1_DC_ODD Output Clock 1 enable Half VCO Shift 0, 1
DYN_CLK_SEL_PIN3 Clock Source - Dynamic Clock - Clock Selector Name Clock name
DYNAMIC_CFG_EN Dynamic Reconfiguration Enable 0, 1
EXT_CLK Clock Source - External Clock EXT_CLK0, EXT_CLK1
EXT_CLK0, EXT_CLK1, EXT_CLK2
FEEDBACK_CLK Use as feedback CLK0, CLK1, CLK2
CLK0, CLK1, CLK2, CLK3, CLK4
FEEDBACK_MODE Feedback Mode INTERNAL, LOCAL, CORE
CORE, LOCAL, EXTERNAL
FRACTIONAL_MODE_EN Fractional Mode Enable 0, 1
FRACTIONAL_COEFFICIENT Fractional Coefficient 0 - 16777215
IS_CLKOUTn_INVERTED Invert the clock output pin 0, 1
LOCKED_PIN Locked Pin Name Pin name
M Multiplier (M) 1 - 255
1, 2, 4
N Pre Divider (N) 1 - 15
1, 2, 4
NAME Instance Name Instance name
O Post Divider (O) 1, 2, 4, 8
1, 2, 4, 8, 16, 32, 64, 128
PHASE_SHIFT_ENA_PIN Phase Shift Enable Pin Name Pin name
PHASE_SHIFT_SEL_PIN Phase Shift Select Pin Name Pin name
PHASE_SHIFT_PIN Phase Shift Pin Name Pin name
PLL_FREQ PLL Frequency Calculated value in MHz
REFCLK_FREQ Reference Clock Frequency (MHz) 10.0 - 50.0
10 - 3304
16 - 8005
REFCLK_SOURCE Clock Source EXTERNAL, CORE, DYNAMIC
RSTN_PIN Reset Pin Name Pin name
RESOURCE PLL Resource Resource name
SSC_MODE Spread Spectrum Clocking Mode DISABLE, STATIC, DYNAMIC
SSC_FREQUENCY SSC Modulation Frequency 30 - 33
SSC_AMPLITUDE SSC Modulation Amplitude 0 - 0.5
SSC_MODULATION_TYPE SSC Spread Direction DOWN, UP, CENTER
USER_SSC_EN_PIN User SSC Enable Pin Name Pin name
VCO_FREQ VCO Frequency Calculated value in MHz
Table 3. Deprecated PLL Properties
API Name Deprecated In Replacement
OUTPUT_CLOCKS_INVERTED 2023.1 CLKOUTn_INVERT_EN
CLKOUTn_INVERT_EN 2024.2 IS_CLKOUTn_INVERTED
1 This API name is new in v2024.1 and will replace CLKOUTn_PHASE_SETTING in a future release.
2 For all Titanium FPGAs except Ti35 and Ti60, and for all Topaz FPGAs except Tz50.
3 If the reference clock source is CORE or DYNAMIC, set this name.
4 The allowed frequency range depends on the clock source you choose. Refer to the data sheet for the Trion FPGA for the PLL timing characteristics.
5 The allowed frequency range depends on the clock source you choose. Refer to the data sheet for the PLL timing characteristics.