Synthesis Options
You can set project-wide synthesis options to control the design flow. You set these options in the Project Editor's Synthesis tab. Most options apply to all FPGA families; however, some are specific to Trion, Topaz, or Titanium FPGAs as shown in the following tables.
| Name | Choices | Description |
|---|---|---|
| --allow-const-ram-index | 0, 1 | Infer RAM if an array is accessed through constant indices. This
option can be useful if memory is written such that a constant index
refers to each segment (e.g., in a byte-enable read/write). See example. 0: Default.
Do not infer. 1: Infer. |
| --blackbox-error | 0, 1 | Generate an error when synthesis encounters an undefined instance or
entity. 0: No error. 1: Default. Generate
error. |
| --blast_const_operand_adders | 0, 1 | If one of the operands to an arithmetic operation is constant,
implement it as logic instead of adders. 0: Disable. 1:
Default. Enable. |
| --bram_output_regs_packing | 0, 1 | Enables the software to pack registers into the output of BRAM.
0: Disable. 1: Default. Enable |
| --bram-push-tco-outreg | 0, 1 | Retime output registers after address decomposition of BRAM to allow
output register packing 0: Default. Disable 1:
Enable |
| --create-onehot-fsms | 0, 1 | Create onehot encoded state machine when appropriate. Synthesis can
only create these state machines if the state variables do not have
explicit encoding in the HDL. If a state machine is coded using onehot
encoding, a new section in the map report
(<project>.map.rpt) shows the encoding
information. See
example. 0: Default. Disabled. 1:
Enabled. |
| --enable_mark_debug | 0, 1 | Write the mark_debug output to <project
dir>/outflow/debug_profile.mark_debug.json
to save debug nets for auto debug probe insertion.0:
Disable. 1: Enable (default) |
| --fanout-limit | 0 to n | If something is high fanout, the tool duplicates the fanout
source. 0: Default. Disable. n: Indicate the fanout
limit at which to begin duplication. |
| --hdl-compile-unit | 0, 1 | When considering multiple source files, resolve `define or parameters
independently or across all files. This option only works with
SystemVerilog files. 0: Across all files. 1: Default.
Independently. |
| --infer-clk-enable | 0, 1, 2, 3, 4 | Infer flip-flop clock enables from control logic. See examples. 0:
disable. 1, 2, 3, 4: Effort levels. |
| --infer-sync-set-reset | 0, 1 | Infer synchronous set/reset signals. 0: Disable. 1:
Default. Enable. |
| --max_ram | -1, 0, n | -1: Default. There is no limit to the number of RAM blocks to
infer. 0: Disable. n: Any
integer. |
| --max_mult | -1, 0, n | -1: Default. There is no limit to the number of multipliers to
infer. 0: Disable. n: Any
integer. |
| --max_threads | -1, n | Choose how many threads that the synthesis tool can launch. -1:
Default. The tool uses the maximum number of available
processors. n: Any integer. |
| --min-sr-fanout | 0, n | Infer the flipflop's synchronous set/reset signal from control logic
if the set/reset signal fanout is greater than n. This option is
useful if the design has a lot of small fanout set/reset signals that
may create routing congestion. 0: Default.
Disable. n: Signal fanout. |
| --min-ce-fanout | 0, n | Infer the flipflops clock enable from c ontrol logic if the clock
enable signal fanout is grester than n. 0: Default.
Disable. n: Signal fanout. |
| --mode | speed, area, area2 | speed: Default. Optimizes for fastest fMAX. area:
Optimizes for smallest area. area2: Uses techniques that
help to optimize large multiplexer trees. |
| --msg_suppression_list | File path | Suppress specific INFO/WARNING messages from synthesis by message
IDs. The suppression list file should contain line separated
message IDs. Comments are supported. The same suppression
list file may be used for both synthesis and place and route.
Unrecognized IDs are ignored. |
| --mult-auto-pipeline | Integer | Performs automatic pipelining for wide multipliers to increase
performance at the cost of extra latency. Inserts pipeline registers at
the output of partial multiplies and partial sums. In Titanium
and Topaz
FPGAs, these pipeline registers can be packed
into the DSP48 blocks as W registers. Additional registers are inserted
at the input and output of the multiplier to balance latency issues
caused by the insertion of the previous registers. The value of this
option determines the number of cycles of latency added as a result
of inserting pipeline registers. When the value is set to 1, 1 set
of pipeline registers are inserted into the wide-multiplier DSP
chain. The pipeline register is inserted after the partial adder
such that the longest path within the wide-multiply DSP chain is
minimized. If the value of this option is set to a number
greater than the number of partial adders in the wide-multiply DSP
chain, pipeline registers are inserted after the multiplier within
the DSP block. Setting this option to a higher value
reduces the longest path of the wide-multiplier at the cost of
higher latency. Note that these registers may not always
be packed into the DSP48 blocks. The maximum value of
--mult-auto-pipeline is equivalent to the number of partial adders
in the wide-multiply DSP chain + 1. If a number greater than the
maximum value is set, synthesis generates a warning message and the
maximum value is used
instead. 0:
Default.
Disable. |
| --mult-decomp-retime | 0, 1 | Perform retiming after decomposition of a wide multiplier to improve
performance. 0: Default. Disable. 1:
Enable. |
| --max-bit-blast-mem-size | 0 - 99999 | Sets the maximum size for memory that is mapped into BRAMs. Memories
exceeding the specified size trigger an error message. Default:
10240 |
| --peri-syn-inference | 0, 1 | Enable unified netlist inference flow. See syn_peri_port for the synthesis attribute that
you use with this option. 0: Default. Disable. 1:
Enable. |
| --peri-syn-instantiation | 0, 1 | Enable unified netlist instantiation flow. See syn_peri_port for the synthesis attribute that
you use with this option. 0: Default. Disable. 1:
Enable. |
| --operator-sharing | 0, 1 | Extract shared operators 0: Default. Disable 1:
Enable |
| --optimize-adder-tree | 0, 1 | Optimize skewed adder trees 0: Default. Disable 1:
Enable |
| --optimize-zero-init-rom | 0, 1 | Opitmize ROMs that are initialized to zero. 0:
Disable 1: Default. Enable |
| --retiming | 0, 1, 2 | Perform retiming optimization. Software moves registers to balance
the combinational delay path. 0: Disable. 1: Default.
Enable. 2: Advanced algorithm that can benefit some
designs. |
| --seq_opt | 0, 1 | Turn on sequential optimization. This option can reduce LUT usage but
may impact fMAX. 0: Disable. 1: Default.
Enable. |
| --seq-opt-sync-only | 0, 1 | Sequential synthesis only considers synchronous reset
flipflops. 0: Default. Consider all flipflops. 1:
Consider synchronous flipflops only. |
| --suppress_info_msgs | off, on | Suppress INFO messages from synthesis. Off:
Default. On: Suppress. |
| --suppress_warning_msgs | off, on | Suppresss WARNING messages from synthesis. Off:
Default. On: Suppress. |
| --use-logic-for-small-mem | 0 to n | Set the size limit of small RAM blocks implemented in LEs. 0: Disable.
64: Default.
|
| --use-logic-for-small-rom | 0 to n | Set the size limit of small ROM blocks implemented in LEs. The number
is the maximum number of LEs used. 0: Disable.
64: Default.
|
| Name | Choices | Description |
|---|---|---|
| --dsp-input-regs-packing | 0, 1 | Allow packing of DSP input registers. 0: Disable. 1:
Default. Enable. |
| --dsp-output-regs-packing | 0, 1 | Allow packing of DSP output registers. 0: Disable. 1:
Default. Enable. |
| --dsp-mac-packing | 0, 1 | Allow multiplier packing, the software packs adder pairs using
multipliers (Trion) or DSP Blocks. 0:
Disable. 1: Default. Enable. |
| --insert-carry-skip | 0, 1 | Enable carry-skip optimization for long adders. This option can be
useful for designs that have long carry chains. It implements the carry
chain with carry skip instead of ripple carry, which can improve
performance at the cost of increased area by splitting the carry chains
into shorter ones. 0: Default. Disabled. 1:
Enable. |
| --pack-luts-to-comb4 | 0, 1, 2 | Pack compatible LUTs into COMB4 primitives. 0: Default.
Disable 1: Effort level 1 2: Effort level
2 |
| Name | Choices | Description |
|---|---|---|
| --mult-input-regs-packing | 0, 1 | Allow packing of multiplier input registers. 0:
Disable. 1: Default. Enable. |
| --mult-output-regs-packing | 0, 1 | Allow packing of multiplier output registers. 0:
Disable. 1: Default. Enable. |