Case Statements with Don't Care (10.9)

VHDL 2008 permits a don’t care, -, in a case? statement.

process(ALL)
begin
    case? A(3 downto 0) is
        when "1---" => c(24) <= '1';
        when "01--" => c(25) <= '1';
        when others => null;
    end case?;
end process;