VHDL 2019 Interface Usage

You can define VHDL 2019 interfaces using record and view definitions. In the following example, a record streaming_bus is defined in the interfaces package. This record defines all the names and types of the elements.

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 

package interfaces is   
    -- record definition
    type streaming_bus is record  
        data_1  : std_logic_vector(3 downto 0);
        data_2  : std_logic_vector(7 downto 0); 
    end record; 
end;

An interface is created for the record streaming_bus using the streaming_master and streaming_slave mode view. You need to define a port mode for each record element. To maximize code reuse, one record can have many mode views.

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 
use work.interfaces.all; -- USING PACKAGE HERE! 

-- Create an interface for the record streaming_bus in the streaming_master mode view 
view streaming_master of streaming_bus is   
    data_1, data_2 : out; 
end view; 

-- Create an interface for the record streaming_bus in the streaming_master mode view 
alias streaming_slave is streaming_master'converse; 

-- streaming_slave is equivalent to: 
--  view streaming_slave of streaming_bus is  
--    data_1, data_2 : in; 
--  end view;

Finally, you can use the streaming_master view for the port declarations.

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 
use work.interfaces.all; -- USING PACKAGE HERE! 

-- source uses "master_interface" as the streaming_master interface
entity source is
    --short form  
    port(clk, rst : in std_logic; master_interface : view streaming_master);    
    -- long form
    -- port(clk, rst : in std_logic; 
    --   master_interface : view streaming_master of streaming_bus);
end;