Revision History
| Date | Version | Description |
|---|---|---|
| February 2026 | 4.5 | Added Sequential Optimization topic. (DOC-2865) |
| November 2025 | 4.4 | Added information on how to use out-of-context (OOC) synthesis
flow. (DOC-2761) Added Hierarchical Names Support.
(DOC-2722) |
| August 2025 | 4.3 | Added warning note to Inferring Wide Multipliers. (DOC-2643) Added --suppress_info_msgs, --suppress_warning_msgs, and
--msg_suppression_list place and route options. (DOC-2599)
|
| May 2025 | 4.2 | Added mark_debug attribute in Synthesis Attributes.
(DOC-2344) Added --enable_mark_debug synthesis
option. |
| February 2025 | 4.1 | Added table of supported SystemVerilog constructs.
(DOC-2342) Updated synthesis options. (DOC-2339) |
| November 2024 | 4.0 | Added additional example for inferring DSP.
(DOC-1623) Added error message EFX-9060 to Post-Synthesis Check Messages.Added --max_threads synthesis
option. (DOC-2051) Added --peri-syn-inference and
--peri-syn-instantiation synthesis options and syn_peri_port
synthesis attribute to support the unified netlist flow.
(DOC-2086) |
| June 2024 | 3.9 |
Added description of VHDL-2019 support for interfaces.
Updated description for --mult-auto-pipeline option.
(DOC-1880)
Added new advanced option for --retiming. (DOC-1880)
Added Warning and Error Messages.
|
| December 2023 | 3.8 | Added the --use-logic-for-small-mem,
--use-logic-for-small-rom, and
--mult-auto-pipeline synthesis options.
(DOC-1484)Corrected quotation marks in the synthesis attribute
examples (now using straight quotes instead of curly).
(DOC-1420) Added topic (Referencing Efinix VHDL Libraries) describing which Efinix VHDL libraries to reference when using Efinix primitives. (DOC-1455) |
| June 2023 | 3.7 | Added syn_keep synthesis attribute.Added
--mult-decomp-retime,
--optimize-zero-init-rom, and
--insert-carry-skip synthesis
options.Provided an example for the
--allow-const-ram-index synthesis
option. |
| May 2023 | 3.6 | Added description about possibility of bit-blasting certain RAM operations but at the cost of FPGA resource. (DOC-1231) |
| December 2022 | 3.5 |
Described synthesis rules for inferring output registers.
(DOC-1020)
Updated the synthesis options. (DOC-1020)
The syn_preserve attribute is not supported on a user hierarchy
instance. (DOC-1020)
Added synthesis pragmas. (DOC-1020)
|
| November 2022 | 3.4 | Added note in "Using VHDL Libraries" about the work library. (DOC-957) |
| August 2022 | 3.3 | Added new synthesis options. (DOC-870) |
| December 2021 | 3.2 | Added new synthesis options. Added more detail about the
Synthesis project settings. (SYN-549) |
| October 2021 | 3.1 | The default for the -blast_const_operand_adders and -seq_opt synthesis options is 1 for Efinity v2021.1 and higher. (DOC-481) |
| June 2021 | 3.0 | Updated for Efinity software v2021.1. Added support for Titanium
FPGAs. Described how to infer Titanium DSP Blocks, shift registers, and
RAM. Added Titanium synthesis
options. Added topic on retiming. Added the syn_srlstyle attribute.
Added the area2 value for the mode synthesis option.
|
| January 2021 | 2.1 | Added information on RAM inferencing. Described the Block RAM
Resource Estimator. |
| December 2020 | 2.0 | Described new support for VHDL libraries. Added async_reg,
skip_ram_init, syn_srlstyle, syn_ramdecomp, and syn_srlstyl synthesis
attributes. |
| June 2020 | 1.0 | Initial release. |