Edit the SPI Active Clock

About this task

An internal oscillator generates the internal clocks the uses during configuration. In SPI active configuration mode, configuration starts operating at the default frequency (10 MHz) and then switches to the user-selected clock to minimize configuration time (assuming the SPI flash device supports the faster fMAX).

You set the configuration clock frequency in the software.

Table 1. Internal Oscillator Clock Settings
SPI Clock Divider Frequency (MHz)
DIV4 20
DIV8 10

To change the clock frequency:

Procedure

  1. Choose File > Edit SPI Active Clock or click the toolbar icon to open the Edit SPI Active Clock Settings dialog box.
  2. Choose the divider value with DIV Select.
  3. Click Apply and Close to save your changes.

Results

You can also set the clock frequency for the project in the Project Editor > Bitstream Generation tab. Any setting you make in the Edit SPI Active Clock Settings dialog box overrides what you set for the project.

Note: T20 (Q144, F324, F400 packages) and T35 (all packages) support negative edge sampling. Click Enabled to turn it on. Then, specify the number of extra clock cycles to insert between the time when the default clock changes to the specified clock and when the FPGA continues configuration. You can add up to 7 extra clock cycles.