Vector Aggregates (9.3.3)

In VHDL 2008, you can use slices in an array aggregation, and you can use aggregates as targets.

c(15 downto 8) <= (others =>'1')                   when A(8) else   --means "11111111"
                  ('1','1','0','1', others =>'0')  when A(9) else   --means "1101000"
                  (11=>'1', others =>'0')          when A(10) else  --means "00001000"
                  ("1101" , others =>'0')        ;                  --means "1101000"

(C(39),C(40))<= A(1 downto 0);            -- C(39) becomes A(1) , C(40) becomes A(0)