MIPI Lane Property Reference

All of these MIPI D-PHY block properties are applicable to the Titanium and Topaz families.

Table 1. MIPI Lane RX Properties
API Name GUI Name RX TX Values
CLKOUT_PIN Byte Clock (core) Pin Name Pin name
CONN_TYPE Connection Type GCLK, RCLK
DELAY Static Mode Output/Input Delay 0 - 63
DELAY_MODE Delay Mode STATIC, DYNAMIC
DLY_ENA_PIN Dynamic Delay Enable Pin Name Pin name
DLY_INC_PIN Dynamic Delay Control Pin Name Pin name
DLY_RST_PIN Delay Reset Pin Name Pin name
FASTCLK_PIN Serial Clock Pin Name Pin name
FIFO Enable Clock Crossing FIFO 0, 1
FIFO_EMPTY_PIN FIFO Empty Pin Name Pin name
FIFO_RD_PIN Enable FIFO Read Pin Name Pin name
GBUF Global Pin Name1 Pin name
HS_ENA_PIN High-Speed Differential Enable Pin Name Pin name
HS_IN_PIN High-Speed Input Pin Name Pin name
HS_OE_PIN High-Speed Output Enable Pin Name Pin name
HS_OUT_PIN High-Speed Output Pin Name Pin name
HS_TERM_PIN High-Speed Termination Enable Pin Name Pin name
LP_N_IN_PIN Low-Power (N) Input Pin Name Pin name
LP_N_OE_PIN Low-Power (N) Output Enable Pin Name Pin name
LP_N_OUT_PIN Low-Power (N) Output Pin Name Pin name
LP_P_IN_PIN Low-Power (P) Input Pin Name Pin name
LP_P_OE_PIN Low-Power (P) Output Enable Pin Name Pin name
LP_P_OUT_PIN Low-Power (P) Output Pin Name Pin name
MODE Mode DATA_LANE, CLOCK_LANE
NAME Instance Name Instance name
RESOURCE MIPI Resource Pin name
REVERSIBLE Enable LP Reverse Communication 0, 1
RST_PIN Reset Pin Name Pin name
SLOWCLK_PIN Parallel Clock Pin Name Pin name
1 GUI is available in CLKMUX under Regional Buffers tab.