Output Receive Clock Delay

This example shows how to set constraints for an output receive clock.

Figure 1. Receive Clock Delay (GPIO Output, Register Bypass)

The SDC constraint formulas for the receive clock delay are:

set_output_delay -clock <clock> -max <max calculation> <ports>
set_output_delay -clock <clock> -min <min calculation> <ports>

The equations are:

<max calculation> = <max board constraint> + GPIO_OUT_max

<min calculation> = <min board constraint> + GPIO_OUT_min

The following example shows how to calculate the delays and set the constraints.

Constraining Output Receive Clock

You want to constrain the dout output with respect to clock clkin with a max board constraint of 4 ns and a min board constraint of 2 ns. The non-registered GPIO configuration data from the Interface Design report file is:

Non-registered GPIO Configuration:
===================================

+---------------+----------+-------------+----------+----------+
| Instance Name | Pin Name |  Parameter  | Max (ns) | Min (ns) |
+---------------+----------+-------------+----------+----------+
|     clkin     |  clkin   | GPIO_CLK_IN |  1.954   |  0.526   |
|      din      |   din    |   GPIO_IN   |  1.954   |  0.526   |
|      dout     |   dout   |   GPIO_OUT  |  4.246   |  1.081   |
+---------------+----------+-------------+----------+----------+

The equations are:

<max calculation> = 4 + 4.246 = 8.246

<min calculation> = 2 + 1.081 = 3.081

The resulting constraints are:

set_output_delay -clock clkin -max 8.246 dout
set_output_delay -clock clkin -min 3.081 dout

Note: The GPIO_CLK_IN delay is accounted for in the set_clock_latency constraint. Therefore, you do not need to include it in the calculation for set_output_delay. Refer to Clock Latency.