Introduction

Closing timing is an important part of the design process. The Efinity® software includes tools and reports to help you understand your design's timing requirements and let you adjust settings to close timing. This document explains how to set timing constraints using a Synopsys Design Constraints (.sdc) file, and discusses synthesis, placement, and routing options to customize the Efinity® flow. Additionally, it describes how to use the Tcl Console and Tcl commands to explore timing and customize your SDC file.

You can explore timing with just an RTL design and an SDC file. This step helps you understand your design's timing requirements in general terms. If you have not built an interface yet, the placer auto-assigns the interface signals, which you can use to set constraints. After you build your interface, the interface signals are constrained according to the assignments you made in the Interface Designer.