Referencing RTL Source Files

Instead of adding your RTL files to your project individually, you may want to reference them. The Efinity software v2024.1 and higher lets you reference your design's source files in a reference file list (.f). With this method, you can update the .f file once and have the changes reflect for all projects that include the .f file.

Save the .f file in the same directory as your RTL source files. Then add the .f file to your project.

The .f file is a text file. Add the source files one per line. Any directories should be relative to the location of the .f file.

module1.v
module2.v
top.v

Add directories you want to include, The Efinity software searches the include directory for files specified with the `include directive. The software can also find modules that are not specified in the source file list. For example, the software can find module m1 specified in m1.v if the file m1.v is located in a specified include directory.

+incdir+<include_directory>

You can also list another .f file:

-f module1.f
-f module2.f
top.v

You can specify the HDL version for the source file. For Verilog HDL files, the available versions are: verilog_95, verilog_2k, sv_05, and sv_09. For VHDL files, the available options are vhdl_1993, vhdl_2008, and vhdl_2019.

file1.v, t:verilog_2k
file2.vhd, t:vhdl_2019

To include a custom VHDL library, use this format:

file1.vhd, l:<custom library>