GPIO Clock Latency

When using a GPIO as a clock source you need to account for the any board delay and the GPIO input buffer delay.

Figure 1. GBUF to Register Delay

The SDC constraint formulas for the receive clock delay are:

set_clock_latency -source -setup <max calculation> <clock ports>
set_clock_latency -source -hold <min calculation> <clock ports>

The equations are:

<max calculation> = <max board constraint> + GPIO_CLK_IN_max

<min calculation> = <min board constraint> + GPIO_CLK_IN_min

The following example shows how to calculate the delays and set the constraints.

Setting GPIO Clock Latency

You need to define the clock latency before the core clock pin clk. This example assumes that the clock and data traces on the board are well matched; therefore, there is no external board delay.

The GPIO clock buffer delays are shown in the Excerpt of <project>.pt_timing.rpt: (non-registered GPIO table):

Non-registered HSIO GPIO Configuration:
========================================

+---------------+----------+-------------+----------+----------+
| Instance Name | Pin Name |  Parameter  | Max (ns) | Min (ns) |
+---------------+----------+-------------+----------+----------+
|      clk      |   clk    | GPIO_CLK_IN |  0.828   |  0.552   |
|       i       |    i     |   GPIO_IN   |  0.828   |  0.552   |
|       o       |    o     |   GPIO_OUT  |  2.205   |  1.470   |
+---------------+----------+-------------+----------+----------+

The <project>.pt.sdc template is:

# Clock Latency Constraints
############################
# set_clock_latency -source -setup <board_max + 0.828> [get_ports {clk}]
# set_clock_latency -source -hold <board_min + 0.552> [get_ports {clk}]

There is no board delay in this example, therefore, the equations are:

<max calculation> = 0 + 0.828 = 0.828

<min calculation> = 0 + 0.552 = 0.552

The resulting constraints are:

set_clock_latency -source -setup 0.828 [get_ports clk]
set_clock_latency -source -hold 0.552 [get_ports clk]