Conditional and Sequential Statements (10.5.3, 10.5.4)

VHDL 2008 supports conditional and selected sequential statements.

DFFwithReset_inst: Process(All) 
begin
    if clk'event and clk='1' then	
        c(26)<= '0' when reset else A(11);  -- c(26) is Q and A(11) is D
    end if;
end process;