syn_peri_port

You apply the syn_peri_port attribute to top-module ports in your RTL. This option allows you control how inference is done on each I/O port. In the default inference flow, synthesis infers I/O registers or I/O buffers on any I/O port if it is possible. The tool prioritizes inferring I/O registers over I/O buffers (i.e., if an EFX_IBUF or EFX_IREG can be inferred for a given input port, an EFX_IREG will be inferred).

Notice: Refer to the Trion®, Topaz, and Titanium Quantum primitives user guides for primitive defintions.

The attribute has the following settings:

  • 0—Do not infer any interface blocks
  • 1—Infer buffers only (EFX_IBUF, EFX_OBUF, EFX_IO_BUF)
  • 2—Infer registers only (EFX_IREG, EFX_OREG)
  • 3—Infer buffers and registers (default value in inference flow)

This attribute is supported in the Efinity software v2024.2 and higher.

Verilog HDL: 
module iregtst_port_attr (clk,i1,o1,i2,o2,i3,o3,i4,o4,i5,o5);
    (* syn_peri_port = 0 *) input clk;
    (* syn_peri_port = 0 *) input i1; 
    (* syn_peri_port = 3 *) output o1; 
    (* syn_peri_port = 2 *) input i2;
VHDL: 
entity top is
port (
   pll_resetn : out std_logic;
   pll_lock : in std_logic;
   clk : in std_logic;
   clk50 : in std_logic; 
);
ATTRIBUTE syn_peri_port : INTEGER;
ATTRIBUTE syn_peri_port OF pll_resetn : SIGNAL IS 0;
ATTRIBUTE syn_peri_port OF pll_lock : SIGNAL IS 0;
ATTRIBUTE syn_peri_port OF clk : SIGNAL IS 0;
ATTRIBUTE syn_peri_port OF clk50 : SIGNAL IS 0;