About Efinity Synthesis
The first stage after you complete your RTL design is synthesis. During synthesis, the compiler takes your design and turns it into a gate-level netlist. The software supports synthesis options and attributes so you can optimize your design.
The software supports the synthesizable subset of the following languages:
- SystemVerilog and Verilog HDL
- VHDL
- Mixed languages (any combination of the above)
Notice: Refer to the Efinity Synthesis User Guide for more
information on synthesis options and attributes as well as design guidelines.