About the <project>.pt.sdc File

When you generate constraints in the Interface Designer, the software creates the <project>.pt.sdc in the outflow directory; this template file has the interface block constraints. You copy and paste these constraints into your project SDC file. Some generated constraints require you to modify them, for example, to add a clock period or name. These constraints are commented out so they do not generate errors if you include them in your SDC file without modifying them.

Important: Do not add the <project>.pt.sdc file to your project! It is re-created every time you generate constraints and any changes you make will be overwritten.

The PLL Constraints section has the create_clock SDC command for all PLL outout clocks. Use these commands as is without modification.

# PLL Constraints
#################
create_clock -period 10.0000 i_hbramClk_fb
create_clock -waveform {1.2500 3.7500} -period 5.0000 i_hbramClk90
...

The GPIO Constraints, HSIO GPIO Constraints, and MIPI RX/TX Lane Constraints sections have constraints for these blocks, some of which are templates that you need to modify.

Use SDC constraints for registered inputs and outputs as is without modification.

For GPIO and LVDS blocks used as clock sources, the Interface Designer includes a create_clock template line. To constrain these clocks, replace <USER_PERIOD> with the clock period and uncomment the line.

Non-registered inputs and outputs also have template lines. Modify them as follows:

  • Replace <CLOCK> with the clock name.
  • (Optional) Replace <clkout_pad> with the reference clock pin name and remove the brackets []. If you do not want to use a reference clock pin, delete [-reference_pin <clkout_pad>]
  • Replace <MAX CALCULATION> and <MIN CALCULATION> with the values you calculate as described in Constraining Unsynchronized Inputs and Outputs.
  • Uncomment the line.
# GPIO Constraints
####################
# create_clock -period <USER_PERIOD> [get_ports {clock}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] 
#    -max <MAX CALCULATION> [get_ports {i_arstn}]
# set_input_delay -clock <CLOCK> [-reference_pin <clkout_pad>] 
#    -min <MIN CALCULATION> [get_ports {i_arstn}]
set_output_delay -clock_fall -clock i_hbramClk90 -reference_pin [get_ports 
   {i_hbramClk90~CLKOUT~75~322}] -max 0.263 [get_ports {hbc_ck_n_LO hbc_ck_n_HI}]
set_output_delay -clock_fall -clock i_hbramClk90 -reference_pin [get_ports 
   {i_hbramClk90~CLKOUT~75~322}] -min -0.140 [get_ports {hbc_ck_n_LO hbc_ck_n_HI}]
set_input_delay -clock i_hbramClk_cal -reference_pin [get_ports 
   {i_hbramClk_cal~CLKOUT~32~322}] -max 0.414 [get_ports {hbc_dq_IN_LO[0] hbc_dq_IN_HI[0]}]
set_input_delay -clock i_hbramClk_cal -reference_pin [get_ports 
   {i_hbramClk_cal~CLKOUT~32~322}] -min 0.276 [get_ports {hbc_dq_IN_LO[0] hbc_dq_IN_HI[0]}]
...

The Clock Latency Constraints section has templates for the set_clock_latency constaint. Clock Latency and Constraining I/O describe how to use these templates.

# Clock Latency Constraints
############################
# set_clock_latency -source -setup <board_max -2.834> [get_ports {clk}]
# set_clock_latency -source -hold <board_min -1.417> [get_ports {clk}]
# set_clock_latency -source -setup <board_max + 1.476> [get_ports {refclk}]
# set_clock_latency -source -hold <board_min + 0.738> [get_ports {refclk}]

The JTAG Timing Report shows the SDC constraints for the JTAG signals. Additionally, you should use set_clock_groups to make the JTAG clocks unrelated to other clocks. 

# JTAG Constraints
####################
# create_clock -period <USER_PERIOD> [get_ports {jtag_inst1_TCK}]
# create_clock -period <USER_PERIOD> [get_ports {jtag_inst1_DRCK}]
set_output_delay -clock jtag_inst1_TCK -max 0.117 [get_ports {jtag_inst1_TDO}]
set_output_delay -clock jtag_inst1_TCK -min -0.075 [get_ports {jtag_inst1_TDO}]
...