Constraining I/O

As discussed earlier, you need to constrain the connections from the interface to the core. All connections between the core and interface are considered to be I/O for timing analysis.

If a given interface block is synchronizing the connection to the core, the Interface Designer SDC template includes the set_input_delay and set_output_delay SDC constraints that you need to use. When it is not synchronized, you need to add external board delays to the values the Interface Designer shows.

Note: For Trion®, Topaz, and Titanium FPGAs, most interface connections are synchronous. The exceptions are GPIO blocks in bypass mode and LVDS blocks in x1 bypass mode.

Constrain I/O pins to be timing-equivalent to a register that is clocked with the real or virtual clock you defined. Then, use the set_input_delay and set_output_delay constraints.

Constraining I/O Pins

In this example, sysclk is a virtual clock.

Figure 1. Clock and I/O Pin Constraint Example

Use these constaints to define the clock and set the delays for the pins:

create_clock -name clk -period 10 [get_ports clk]
create_clock -name sysclk -period 10
set_input_delay -clock sysclk -max 2.4 [get_ports ina]
set_output_delay -clock sysclk -max 1.2 [get_ports outa]