Expressions in Port Maps (11.8)
VHDL 2008 allows expressions in port maps.
inst1 : entity work.test1(behave)
port map (A=>(B(13) AND A(13)), B=> B(15),C=>C(41));VHDL 2008 allows expressions in port maps.
inst1 : entity work.test1(behave)
port map (A=>(B(13) AND A(13)), B=> B(15),C=>C(41));