PLL External Feedback Clock Latency

When using a PLL as a clock source you need to account for the any board delay, the GPIO input buffer delay (for the PLL's reference clock pin), and the PLL compensation delay.

Note: Trion FPGAs do not have external feeddback mode.
Figure 1. External Feedback Mode Delay

When the PLL is in external feedback mode, the compensation delay is equal to GPIO_IN plus the clock network delay plus GPIO_CLK_OUT.

The SDC constraint formulas for the receive clock delay are:

set_clock_latency -source -setup <max calculation> <clock ports>
set_clock_latency -source -hold <min calculation> <clock ports>

The equations are:

<max calculation> = <max board constraint> + GPIO_INmax - <PLL compensation>

<min calculation> = <min board constraint> + GPIO_INmin - <PLL compensation>

The Efinity software v2023.2 and higher calculates the GPIO input buffer and PLL compensation delays and provides them in a template in the <project>.pt.sdc file. You still need to add any board delays if needed.

The following example shows how to calculate the delays and set the constraints.

Setting PLL External Feedback Clock Latency

In this example, the PLL clock output is called clk. This example assumes that the clock and data traces on the board are well matched; therefore, there is no external board delay.
Excerpt of <project>.pt_timing.rpt:
+--------+----------+-----------+-...-+------------------+------------------+
| PLL    | Resource | Reference | ... | PLL Compensation | PLL Compensation |
|Instance|          |   Clock   | ... | Delay Max (ns)   | Delay Min (ns)   |
+--------+----------+-----------+-...-+------------------+------------------+
|  pll   | PLL_BL0  | external  | ... |       5.379      |        3.541     |
+--------+----------+-----------+-...-+------------------+------------------+
 
+-------+-------------+----------------------------+-----------------------+----------+
| Clock | Period (ns) | Enable Dynamic Phase Shift | Phase Shift (degrees) | Inverted |
+-------+-------------+----------------------------+-----------------------+----------+
|  clk  |   10.0000   |           False            |          0.0          |  false   |
+-------+-------------+----------------------------+-----------------------+----------+
 
---------- PLL Timing Report (end) ----------
 
---------- 2.1 HSIO GPIO Timing Report (begin) ----------
 
Clkout GPIO Configuration:
===========================
 
+---------------+-----------+--------------+----------+----------+--------------------+
| Instance Name | Clock Pin |  Parameter   | Max (ns) | Min (ns) | Reference Pin Name |
+---------------+-----------+--------------+----------+----------+--------------------+
|     clkout    |    clk    | GPIO_CLK_OUT |  2.205   |  1.470   |  clk~CLKOUT~18~1   |
|     refclk    |  refclk   |  GPIO_IN     |  0.828   |  0.552   |                    |
|    pll_fbk    |  pll_fbk  |  GPIO_IN     |  0.828   |  0.552   |                    |
+---------------+-----------+--------------+----------+----------+--------------------+
The <project>.pt.sdc template is:
# Clock Latency Constraints
############################
# set_clock_latency -source -setup <board_max -4.551> [get_ports {clk}]
# set_clock_latency -source -hold <board_min -2.989> [get_ports {clk}]
The equations are:
<max calculation> = 0 - 4.551 = -4.551
<min calculation> = 0 - 2.989 = -2.989
The numbers are negative because the PLL compensation is so much larger than the input delay.
The resulting constraints are:
set_clock_latency -source -setup -4.551 [get_ports clk]
set_clock_latency -source -hold -2.989 [get_ports clk]