| GBUF |
Global Pin Name1 |
|
 |
 |
Pin name |
| RX_CONN_TYPE |
Connection Type |
 |
|
|
NORMAL, PLL_CLKIN |
|
 |
 |
NORMAL, GCLK, RCLK, PLL_CLKIN, PLL_EXTFB |
| RX_DBG_PIN |
DPA Debug Bus Name |
|
 |
 |
Pin name |
| RX_DELAY |
Static Mode Delay Setting |
|
 |
 |
0 - 63 |
| Static Delay Setting |
 |
|
|
0 - 63 |
| RX_DELAY_MODE |
Delay Mode |
|
 |
 |
STATIC, DYNAMIC, DPA |
| RX_DESER |
Serialization Width |
 |
|
|
2, 3, 4, 5, 6, 7, 8 |
|
 |
 |
1, 2, 3, 4, 5, 6, 7, 8, 10 |
| RX_DLY_ENA_PIN |
Dynamic Enable Pin Name |
|
 |
 |
Pin name |
| RX_DLY_INC_PIN |
Dynamic Delay Control Pin Name |
|
 |
 |
Pin name |
| RX_DLY_RST_PIN |
Dynamic Reset Delay Pin Name |
|
 |
 |
Pin name |
| RX_EN_DELAY |
Enable Delay Setting |
 |
|
|
0, 1 |
| RX_EN_DESER |
Enable Deserialization |
 |
 |
 |
0, 1 |
| RX_ENA_PIN |
Enable Pin Name |
|
 |
 |
Pin name |
| RX_FASTCLK_PIN |
Serial Clock Pin Name |
 |
 |
 |
Pin name |
| RX_FIFO |
Enable Clock Crossing FIFO |
|
 |
 |
0, 1 |
| RX_FIFO_EMPTY_PIN |
FIFO Empty Pin Name |
|
 |
 |
Pin name |
| RX_FIFO_RD_PIN |
Enable FIFO Read Pin Name |
|
 |
 |
Pin name |
| RX_FIFOCLK_PIN |
FIFO Clock Pin Name |
|
 |
 |
Pin name |
| RX_HALF_RATE |
Enable Half Rate Serialization |
|
 |
 |
0, 1 |
| RX_IN_PIN |
Input Pin/Bus Name |
 |
 |
 |
Pin name |
| RX_LOCK_PIN |
DPA Lock Pin Name |
|
 |
 |
Pin name |
| RX_RST_PIN |
Reset Pin Name |
|
 |
 |
Pin name |
| RX_SLOWCLK_PIN |
Parallel Clock Pin Name |
 |
 |
 |
Pin name |
| RX_TERM |
Termination |
|
 |
 |
ON, OFF, DYNAMIC |
| On-Die LVDS Termination |
 |
|
|
0, 1 |
| RX_TERM_PIN |
Termination Pin Name |
|
 |
 |
Pin name |
| RX_VOC_DRIVER |
Enable Output Common Mode Driver |
|
 |
 |
0, 1 |