Constraining Unsynchronized Inputs and Outputs
Unsynchronized inputs and outputs are simple GPIO blocks in bypass mode or LVDS blocks in
x1 bypass mode. For these blocks, you need to factor in any external board delays when
calculating the -min and -max values for the input and
output delays.
- A receive clock is generated outside of the FPGA and is passed to the FPGA through a GPIO pin.
- A forward clock is generated by the FPGA and sent off chip though a GPIO pin in clock out mode.
For unsynchronized input or output signals, the GPIO block bypasses the register.
GPIO_IN represents a combinational delay from the pad through the
I/O buffer. GPIO_OUT represents a combinational delay to
the pad through the I/O buffer from either the output or output enable signals.
- Determine which mode you are constraining (input receive, input forward, output receive, or output forward).
- Find the mininum (fast) and maximum (slow) timing values in the Interface Designer report file <design name>.pt_timing.rpt.
- Use formulas (provided in later sections) to calculate the delay.
- Add the constraint to your SDC file.
Receive Clock
A receive clock is passed to the FPGA design by configuring a GPIO in input mode and and
setting the connection type to GCLK or RCLK. GPIO_IN_CLK represents the
combinational delay from the pad through the I/O buffer to the global clock tree.
Forward Clock Using GPIO in clkout Mode
A forward clock is generated by the FPGA design and sent off chip by configuring a
GPIO in clkout mode. GPIO_CLK_OUT represents
the combinational delay through the FPGA clock tree and the I/O buffer to
the pad.
Forward Clock Using GPIO in output Mode
Sometimes the clock generated by the FPGA is only used in the external system and is not a clock in the FPGA design. In this case, you use a regular GPIO block in output mode to forward the clock off chip.
