Example: FPGA Forwarded Clock

The following figure illustrates how to use a generated clock as a forward clock. The generated clock, ADC_1_SCLK, is generated from the PLL output PLL_sCLK50 in the interface. ADC_1_SCLK is a forward clock to clock an off-chip flipflop outside the FPGA. The flipflop generates another signal, ADC_1_DOUT, that inputs back to the core.

Figure 1. Generated Clock Forward Clock Example

SDC Commands

create_clock -name {outclk_0_pll}  -period 20 [get_ports PLL_sCLK50]
create_generated_clock -name ADC_1_SCLK -source [get_ports PLL_sCLK50] -divide_by 4 ADC_1_SCLK
set_input_delay -clock [get_clocks ADC_1_SCLK] -reference_pin [get_ports ADC_1_SCLK] \
    -max 24.000 [get_ports ADC_1_DOUT]
set_input_delay -clock [get_clocks ADC_1_SCLK] -reference_pin [get_ports ADC_1_SCLK] \
    -min 4.000 [get_ports ADC_1_DOUT]