Ethernet SGMII Property Reference

These SGMII block properties are only applicable to Titanium FPGAs with transceivers. Refer to the data sheet for which packages have transceivers.

Table 1. Base Properties

API Name	GUI Name	Values
NAME	Instance Name	Instance name
RESOURCE	SGMII Resource	Resource

Table 2. Control Register Properties

API Name	GUI Name	Values
SS_1GBE_DATA_RATE_LANE_NID	Data Rate	"10/100/1000 Mbps", "2.5 Gbps"
SW_1GBE_ACTIVITY_LANE_NID	Enable Activity Status for LED	['0','1']
1G_PCS_L_NID__PCS_CONTROL__ENABLE_AUTO_NEG	Enable SGMII Auto Negotiation (AN)	['0','1']

Table 3. Clock and Reset Properties

API Name	GUI Name	Values
LN_1GBE_CONN_TYPE	Interface Clock Input Connection Type	gclk, rclk
LN_1GBE_X2_CONN_TYPE	Interface Clock X2 Input Connection Type	gclk, rclk
1GBE_CLK_PIN	Interface Clock Input Pin Name	Pin name
1GBE_CLK_X2_PIN	Interface Clock X2 Input Pin Name	Pin name
PCS_RST_N_RX_PIN	PCS Receive Reset Pin Name	Pin name
PCS_RST_N_TX_PIN	PCS Transmit Reset Pin Name	Pin name
PHY_RESET_N_PIN	PHY Lane Reset Pin Name	Pin name

Table 4. Control Properties

API Name	GUI Name	Values
PMA_TX_ELEC_IDLE_PIN	PMA Transmit Electrical Idle Pin Name	Pin name

Table 5. Error and Status Properties

API Name	GUI Name	Values
CTC_ERR_PIN	CTC Error Pin Name	Pin name
PHY_INTERRUPT_PIN	PHY Interrupt Pin Name	Pin name
RX_ACTIVITY_PIN	Receive Activity Pin Name	Pin name
SYNC_STATUS_PIN	Sync Status Pin Name	Pin name
TX_ACTIVITY_PIN	Transmit Activity Pin Name	Pin name

Table 6. Power Up Properties

API Name	GUI Name	Values
PMA_XCVR_PLLCLK_EN_ACK_PIN	Link PLL Clock Enable Acknowledge Pin Name	Pin name
PMA_XCVR_PLLCLK_EN_PIN	Link PLL Clock Enable Pin Name	Pin name
PMA_XCVR_POWER_STATE_ACK_PIN	Link Power State Acknowledge [3:0] Bus Name	Bus name
PMA_XCVR_POWER_STATE_REQ_PIN	Link Power State Request [3:0] Bus Name	Bus name
PMA_RX_SIGNAL_DETECT_PIN	PMA Receiver Signal Detect Pin Name	Pin name

Table 7. SGMII Properties

API Name	GUI Name	Values
PCS_AN_COMPLETE_PIN	PCS Auto Negotiation Complete Pin Name	Pin name
GMII_RX_DV_PIN	Receive GMII Control [1:0] Bus Name	Bus name
GMII_RXD_PIN	Receive GMII Data [15:0] Bus Name	Bus name
GMII_RX_ER_PIN	Receive GMII Error [1:0] Bus Name	Bus name
SGMII_MODE_PIN	SGMII Mode [1:0] Bus Name	Bus name
GMII_TXD_PIN	Transmit GMII Data [15:0] Bus Name	Bus name
GMII_TX_EN_PIN	Transmit GMII Enable [1:0] Bus Name	Bus name
GMII_TX_ER_PIN	Transmit GMII Error [1:0] Bus Name	Bus name

Table 8. Common Properties: APB

API Name	GUI Name	Values
USER_APB_CLK_PIN	APB Clock Pin Name	Pin name
USER_APB_CLK_INVERT_EN	Invert APB Clock Pin	1, 0
USER_APB_PADDR_PIN	APB Address [23:0] Bus Name	Bus name
USER_APB_PENABLE_PIN	APB Enable Pin Name	Pin name
USER_APB_PRDATA_PIN	APB Read Data [31:0] Bus Name	Bus name
USER_APB_PREADY_PIN	APB Ready Pin Name	Pin name
USER_APB_PSEL_PIN	APB Select Pin Name	Pin name
USER_APB_PWDATA_PIN	APB Write Data [31:0] Bus Name	Bus name
USER_APB_PWRITE_PIN	APB Write Pin Name	Pin name

Table 9. Common Properties: Clock and Reset

API Name	GUI Name	Values
PHY_RESET_EN	Enable PHY Quad Reset Pin	0, 1
PHY_CMN_RESET_N_PIN	PHY Quad Reset Pin Name	Pin name

Table 10. Common Properties: Error and Status

API Name	GUI Name	Values
LED_TICK_TOGGLE_PIN	LED Tick Toggle Pin Name	Pin name
PMA_CMN_READY_PIN	PHY Ready Pin Name	Pin name

Table 11. Common Properties: Configuration

API Name	GUI Name	Values
COMMON_INST_NAME	Common Instance Name	Read only1
SW_1GBE_REMOVE_PREAMBLE	Remove 1 Preamble Byte for Even Number of Idles	0, 1

Table 12. Common Properties: Reference Clock

API Name	GUI Name	Values
PLL_LC_CONN	Common PLL Connection	Refclk 0, Refclk 0 and 1
SS_REFCLK_FREQ	Reference Clock 0 Frequency (MHz)	62.5, 100, 156.25
PIPE_CONFIG_CMN__CONFIG_REG_2__​PMA_CMN_REFCLK_SEL	Reference Clock 0 Source	External
PIPE_CONFIG_CMN__CONFIG_REG_2__​PMA_CMN_REFCLK_TERMEN	Enable 50 Ω to ground on-die termination for REFCLK0	0, 1
SS_REFCLK_FREQ_2	Reference Clock 0 Frequency (MHz)	62.5, 100, 156.25
PIPE_CONFIG_CMN__CONFIG_REG_2__​PMA_CMN_REFCLK1_SEL	Reference Clock 1 Source	External
PIPE_CONFIG_CMN__CONFIG_REG_2__​PMA_CMN_REFCLK1_TERMEN	Enable 50 Ω to ground on-die termination for REFCLK1	0, 1
SS_REFCLK_ONBOARD_OSC	Reference clock from on-board crystal	0, 1
REFCLK_SEL	Reference Clock Select	Refclk 0, Refclk 1
SS_REFCLK_FREQ	Reference Clock 0 Frequency (MHz)	19.19:156.28
PIPE_CONFIG_CMN__CONFIG_REG_2__​PMA_CMN_REFCLK_SEL	Reference Clock 0 Source	External, Internal
REF_CLK_INTERNAL_SRC	Internal Source	Core, PLL
PMA_CMN_REFCLK_CORE_PIN	PMA Core Reference Clock Pin Name
SS_REFCLK_FREQ_2	Reference Clock 1 Frequency (MHz)	19.19:156.28
PIPE_CONFIG_CMN__CONFIG_REG_2__​PMA_CMN_REFCLK1_SEL	Reference Clock 1 Source	External, Internal
REF_CLK1_INTERNAL_SRC	Internal Source	Core, PLL
PMA_CMN_REFCLK1_CORE_PIN	PMA Core Reference Clock Pin Name