syn_extract_enable

You use this signal attribute on register outputs. To use this attribute, set it to (false, no, or 0). During synthesis, the software will not infer an active clock enable (except when there is a gated clock) on registers with this attribute set.

Verilog HDL:

(* syn_extract_enable="false" *) reg [3:0] cnt;

VHDL:

attribute syn_extract_enable: boolean;
attribute syn_extract_enable of cnt : signal is false;