Critical Paths

The final two report sections show the path detail reports for the maximum (setup) and minimum (hold) critical paths. The report only shows the most critical path for each relationship. To see additional paths, use the report_timing Tcl command (see report_timing Command). A typical path report consists of the following sections:

  • Header—Specifies the launch and capture clock domains.
  • Path summary—Lists the start and end points of a given path. It also shows the launch and capture clock information as well as the associatged clock edges, the slack, and a summary of the arrival and required time calculations.
  • Launch clock path—The path the clock signals takes.
  • Data path—The path the data signal takes
  • Capture clock path—The path the capture clock takes.

The following example shows a snippet of the report for Oclk.

Max Critical Path, Detail Report

################################################################################
Path Detail Report (Oclk vs Oclk)
################################################################################


++++ Path 1 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

Path Begin    : Oled[2]~FF|CLK                          
Path End      : Oled[3]~FF|D                            
Launch Clock  : Oclk (RISE)                             
Capture Clock : Oclk (RISE)                             
Slack         : 99999.408 (required time - arrival time)
Delay         : 0.358                                   

Logic Level             : 1
Non-global nets on path : 1
Global nets on path     : 0

Launch Clock Path Delay        : 2.342
+ Clock To Q + Data Path Delay : 0.474
--------------------------------------
End-of-path arrival time       : 2.816

Constraint                     :  99999.992
+ Capture Clock Path Delay     :      2.342
- Clock Uncertainty            :      0.110
-------------------------------------------
End-of-path required time      : 100002.224

Launch Clock Path
     name       model name   delay (ns)  cumulative delay (ns) pins on net    location
========================================================================================
Oclk              inpad        0.000             0.000              0        (334,318)
Oclk              inpad        0.110             0.110              6        (334,318)
Oclk              net          2.232             2.342              6        (334,318)
   Routing elements:
      Manhattan distance of X:214, Y:314
Oled[2]~FF|CLK    ff           0.000             2.342              6        (120,4)  

Data Path
    name       model name   delay (ns)  cumulative delay (ns) pins on net    location
=======================================================================================
Oled[2]~FF|Q      ff          0.113             0.113              4         (120,4)
Oled[2]           net         0.304             0.417              4         (120,4)
   Routing elements:
      Manhattan distance of X:0, Y:1
LUT__77|in[2]     lut         0.054             0.471              4         (120,5)
LUT__77|out       lut         0.000             0.471              2         (120,5)
Oled[3]~FF|D      ff          0.003             0.474              2         (120,5)

Capture Clock Path
     name       model name   delay (ns)  cumulative delay (ns) pins on net    location
========================================================================================
Oclk              inpad        0.000             0.000              0        (334,318)
Oclk              inpad        0.110             0.110              6        (334,318)
Oclk              net          2.232             2.342              6        (334,318)
   Routing elements:
      Manhattan distance of X:214, Y:313
Oled[3]~FF|CLK    ff           0.000             2.342              6        (120,5)