About Constraints

The Efinity® software supports the Synopsys Design Constraints format for specifying timing constraints. The software validates the timing performance of your design's core logic using industry-standard constraint, analysis, and reporting methodology. During compilation, the software generates a timing analysis report. The pins, nets, and ports used with SDC constraints refer to the post-synthesis netlist.

Trion®, Topaz, and Titanium FPGAs feature interface blocks—I/O logic and buffers, I/O banks, PLLs, etc.—that connect the core logic to the package pins. You use the Efinity® Interface Designer to configure these interface blocks for your design. After you configure these blocks, you generate a constraint template file (<project>.pt.sdc) that you use as the basis for your design's SDC file. You can also refer to report files for the interface blocks, which you can view in the Results tab under the Efinity® Dashboard.

  • For synchronous (registered) interfaces, the template defines clocks and sets input and output delays for your design. You simply copy and paste the relevant lines from the SDC template file to your own SDC file and adjust the timing as needed.
  • For non-synchronous (unregistered) interfaces, you need to determine the interface timing and board timing and add those to your core settings.
Important: Unlike traditional FPGAs, with Trion®, Topaz, and Titanium FPGAs you make timing constraints at the core level, not the interface or package level.
Efinix recommends that you use registered interfaces as much as possible to simplify the SDC constraints you need.

Figure 1. Set Constraints at the Core Level

Note: Refer to SDC Constraints (Alphabetical) for a list of supported SDC constraints and object specifiers.