PCIe Property Reference

These PCIe block properties are only applicable to Titanium FPGAs with transceivers. Refer to the data sheet for which packages have transceivers.

Note: Mode is root port (RP), endpoint (EP), or All (root port and end point).
Table 1. Base
GUI Name API Name Mode Values
Instance Name NAME All Instance name
PCIe Resource RESOURCE All Recource name
Mode PIPE_CONFIG_CMN__CONFIG_REG_0__​MODE_SELECT All 'Endpoint', 'Root Port'
Link Width PIPE_CONFIG_CMN__CONFIG_REG_0__​LANE_COUNT_IN All 'x1', 'x2', 'x4'
Generation PIPE_CONFIG_CMN__CONFIG_REG_0__​PCIE_GENERATION_SEL All 'Gen1', 'Gen2', 'Gen3', 'Gen4'
Maximum Payload Size I_CLIENT_RC__I_PCIE_CAP__MP RP '128 bytes', '256 bytes', '512 bytes'
Maximum Payload Size SS_PCIE_MPS EP '128 bytes', '256 bytes', '512 bytes'
Gen3 Equalization RX Preset SS_PCIE_GEN3_RX_PRESET RP 0x0 - 0x6
Gen3 Equalization TX Preset SS_PCIE_GEN3_TX_PRESET RP 0x0 - 0xa
Gen4 Equalization TX Preset SS_PCIE_GEN4_TX_PRESET RP 0x0 - 0xa
SRIS Enable SS_PCIE_SRIS_EN All 0, 1
Force device to enter compliance mode SS_PCIE_COMPLIANCE_EN All 0, 1
Table 2. Reference Clock
GUI Name API Name Mode Values
Reference Clock Frequency REF_CLK_FREQUENCY All 16.0 - 500.0
Reference Clock Source PIPE_CONFIG_CMN__CONFIG_REG_2__​PMA_CMN_REFCLK_SEL All 'External'
External Clock PMA_CMN__CMN_PLLLC_GEN_PREG__​CMN_PLLLC_PFDCLK1_SEL_PREG All 'Refclk 0'
Enable 50 Ω to ground on-die termination for REFCLK0 PIPE_CONFIG_CMN__CONFIG_REG_2__​PMA_CMN_REFCLK_TERMEN All 0, 1
Reference clock from on-board crystal SS_REFCLK_ONBOARD_OSC EP 0, 1
Table 3. Reset
GUI Name API Name Mode Values
Hot Reset Input Pin Name HOT_RESET_IN_PIN RP Pin name
Hot Reset Output Pin Name HOT_RESET_OUT_PIN EP Pin name
Link Down Reset Pin Name LINK_DOWN_RESET_OUT_PIN All Pin name
Reset Acknowledge Pin Name RESET_ACK_PIN All Pin name
Reset Request Pin Name RESET_REQ_PIN All Pin name
Table 4. Function
GUI Name API Name Mode Values
ARI Enable PIPE_CONFIG_CMN__CONFIG_​REG_0__ARI_ENABLE All 0, 1
BAR0 Aperture I_CLIENT_LM__I_RC_BAR_​CONFIG_REG__RCBAR0A RP '1 GB', '1 KB', '1 MB', '128 B', '128 GB', '128 KB', '128 MB', '16 B', '16 GB', '16 KB', '16 MB', '2 GB', '2 KB', '2 MB', '256 B', '256 GB', '256 KB', '256 MB', '32 B', '32 GB', '32 KB', '32 MB', '4 B', '4 GB', '4 KB', '4 MB', '512 B', '512 KB', '512 MB', '64 B', '64 GB', '64 KB', '64 MB', '8 B', '8 GB', '8 KB', '8 MB'
BAR0 Control I_CLIENT_LM__I_RC_BAR_​CONFIG_REG__RCBAR0C RP '32 bit I/O BAR', '32 bit non-prefetchable memory BAR', '32 bit prefetchable memory BAR', '64 bit non-prefetchable memory BAR', '64 bit prefetchable memory BAR', 'Disabled'
BAR1 Aperture I_CLIENT_LM__I_RC_BAR_​CONFIG_REG__RCBAR1A RP '1 GB', '1 KB', '1 MB', '128 B', '128 KB', '128 MB', '16 B', '16 KB', '16 MB', '2 GB', '2 KB', '2 MB', '256 B', '256 KB', '256 MB', '32 B', '32 KB', '32 MB', '4 B', '4 KB', '4 MB', '512 B', '512 KB', '512 MB', '64 B', '64 KB', '64 MB', '8 B', '8 KB', '8 MB'
BAR1 Control I_CLIENT_LM__I_RC_BAR_​CONFIG_REG__RCBAR1C RP '32 bit I/O BAR', '32 bit non-prefetchable memory BAR', '32 bit prefetchable memory BAR', 'Disabled'
Class Code I_CLIENT_RC__I_REVISION_​ID_CLASS_CODE__PIB RP 0x0 - 0xff
Device ID I_CLIENT_RC__I_VENDOR_​ID_DEVICE_ID__DID RP 0x0 - 0xffff
Enable SRIOV PIPE_CONFIG_CMN__CONFIG_​REG_0__SR_IOV_ENABLE EP 0, 1
PF0 VF Count I_CLIENT_PF0__I_FUNC_DEP_​LINK_NUMVFS_REG__NVF EP 0 - 64
PF1 VF Count I_CLIENT_PF1__I_FUNC_DEP_​LINK_NUMVFS_REG__NVF EP 0 - 64
PF2 VF Count I_CLIENT_PF2__I_FUNC_DEP_​LINK_NUMVFS_REG__NVF EP 0 - 64
PF3 VF Count I_CLIENT_PF3__I_FUNC_DEP_​LINK_NUMVFS_REG__NVF EP 0 - 64
Programming Interface Byte I_CLIENT_RC__I_REVISION_​ID_CLASS_CODE__CC RP 0x0 - 0xff
Revision ID I_CLIENT_RC__I_REVISION_​ID_CLASS_CODE__RID RP 0x0 - 0xff
Sub-Class Code I_CLIENT_RC__I_REVISION_​ID_CLASS_CODE__SCC RP 0x0 - 0xff
Subsystem Vendor ID I_CLIENT_LM__I_VENDOR_​ID_REG__SVID All 0x0 - 0xffff
Total Physical Functions SS_PCIE_PF_NUM EP 1 - 4
Vendor ID I_CLIENT_LM__I_VENDOR_​ID_REG__VID All 0x0 - 0xffff
Table 5. Physical Function n
GUI Name API Name Mode Values
BAR0 Aperture I_CLIENT_LM__I_PF_n_BAR_​CONFIG_0_REG__BAR0A EP '1 GB', '1 KB', '1 MB', '128 B', '128 GB', '128 KB', '128 MB', '16 GB', '16 KB', '16 MB', '2 GB', '2 KB', '2 MB', '256 B', '256 GB', '256 KB', '256 MB', '32 GB', '32 KB', '32 MB', '4 GB', '4 KB', '4 MB', '512 B', '512 KB', '512 MB', '64 GB', '64 KB', '64 MB', '8 GB', '8 KB', '8 MB'
BAR0 Control I_CLIENT_LM__I_PF_n_BAR_​CONFIG_0_REG__BAR0C EP '32 bit I/O BAR', '32 bit non-prefetchable memory BAR', '32 bit prefetchable memory BAR', '64 bit non-prefetchable memory BAR', '64 bit prefetchable memory BAR', 'Disabled'
BAR1 Aperture I_CLIENT_LM__I_PF_n_BAR_​CONFIG_0_REG__BAR1A EP '1 GB', '1 KB', '1 MB', '128 B', '128 KB', '128 MB', '16 KB', '16 MB', '2 GB', '2 KB', '2 MB', '256 B', '256 KB', '256 MB', '32 KB', '32 MB', '4 KB', '4 MB', '512 B', '512 KB', '512 MB', '64 KB', '64 MB', '8 KB', '8 MB'
BAR1 Control I_CLIENT_LM__I_PF_n_BAR_​CONFIG_0_REG__BAR1C EP '32 bit I/O BAR', '32 bit non-prefetchable memory BAR', '32 bit prefetchable memory BAR', 'Disabled'
BAR2 Aperture I_CLIENT_LM__I_PF_n_BAR_​CONFIG_0_REG__BAR2A EP '1 GB', '1 KB', '1 MB', '128 B', '128 GB', '128 KB', '128 MB', '16 GB', '16 KB', '16 MB', '2 GB', '2 KB', '2 MB', '256 B', '256 GB', '256 KB', '256 MB', '32 GB', '32 KB', '32 MB', '4 GB', '4 KB', '4 MB', '512 B', '512 KB', '512 MB', '64 GB', '64 KB', '64 MB', '8 GB', '8 KB', '8 MB'
BAR2 Control I_CLIENT_LM__I_PF_n_BAR_​CONFIG_0_REG__BAR2C EP '32 bit I/O BAR', '32 bit non-prefetchable memory BAR', '32 bit prefetchable memory BAR', '64 bit non-prefetchable memory BAR', '64 bit prefetchable memory BAR', 'Disabled'
BAR3 Aperture I_CLIENT_LM__I_PF_n_BAR_​CONFIG_0_REG__BAR3A EP '1 GB', '1 KB', '1 MB', '128 B', '128 KB', '128 MB', '16 KB', '16 MB', '2 GB', '2 KB', '2 MB', '256 B', '256 KB', '256 MB', '32 KB', '32 MB', '4 KB', '4 MB', '512 B', '512 KB', '512 MB', '64 KB', '64 MB', '8 KB', '8 MB'
BAR3 Control I_CLIENT_LM__I_PF_n_BAR_​CONFIG_0_REG__BAR3C EP '32 bit I/O BAR', '32 bit non-prefetchable memory BAR', '32 bit prefetchable memory BAR', 'Disabled'
BAR4 Aperture I_CLIENT_LM__I_PF_n_BAR_​CONFIG_1_REG__BAR4A EP '1 GB', '1 KB', '1 MB', '128 B', '128 GB', '128 KB', '128 MB', '16 GB', '16 KB', '16 MB', '2 GB', '2 KB', '2 MB', '256 B', '256 GB', '256 KB', '256 MB', '32 GB', '32 KB', '32 MB', '4 GB', '4 KB', '4 MB', '512 B', '512 KB', '512 MB', '64 GB', '64 KB', '64 MB', '8 GB', '8 KB', '8 MB'
BAR4 Control I_CLIENT_LM__I_PF_n_BAR_​CONFIG_1_REG__BAR4C EP '32 bit I/O BAR', '32 bit non-prefetchable memory BAR', '32 bit prefetchable memory BAR', '64 bit non-prefetchable memory BAR', '64 bit prefetchable memory BAR', 'Disabled'
BAR5 Aperture I_CLIENT_LM__I_PF_n_BAR_​CONFIG_1_REG__BAR5A EP '1 GB', '1 KB', '1 MB', '128 B', '128 KB', '128 MB', '16 KB', '16 MB', '2 GB', '2 KB', '2 MB', '256 B', '256 KB', '256 MB', '32 KB', '32 MB', '4 KB', '4 MB', '512 B', '512 KB', '512 MB', '64 KB', '64 MB', '8 KB', '8 MB'
BAR5 Control I_CLIENT_LM__I_PF_n_BAR_​CONFIG_1_REG__BAR5C EP '32 bit I/O BAR', '32 bit non-prefetchable memory BAR', '32 bit prefetchable memory BAR', 'Disabled'
Class Code I_CLIENT_PFn__I_REVISION_​ID_CLASS_CODE__CC EP 0x0 - 0xff
Device ID I_CLIENT_PFn__I_VENDOR_​ID_DEVICE_ID__DID EP 0x0 - 0xffff
Expansion ROM BAR Aperture SS_PCIE_PFn_EXP_ROM_BAR EP '1 MB', '128 KB', '16 KB', '16 MB', '2 KB', '2 MB', '256 KB', '32 KB', '4 KB', '4 MB', '512 KB', '64 KB', '8 KB', '8 MB', 'Disabled'
Interrupt Pin SS_PCIE_PFn_LEGACY_INT_PIN EP 'INTA', 'INTB', 'INTC', 'INTD', 'NO INT'
MSI Multiple Message Capable I_CLIENT_PFn__I_MSI_CTRL_​REG__MMC EP '1', '16', '2', '32', '4', '8'
MSI-X BAR Indicator I_CLIENT_PFn__I_MSIX_TBL_​OFFSET__BARI EP 'BAR0', 'BAR1', 'BAR2', 'BAR3', 'BAR4', 'BAR5'
MSI-X Capability ID I_CLIENT_PFn__I_MSIX_CTRL__​CID EP 0x0 - 0xff
MSI-X Capabilities Pointer I_CLIENT_PFn__I_MSIX_CTRL__​CP EP 0x0 - 0xff
MSI-X PBA Indicator I_CLIENT_PFn__I_MSIX_PENDING_​INTRPT__BARI1 EP 'BAR0', 'BAR1', 'BAR2', 'BAR3', 'BAR4', 'BAR5'
MSI-X PBA Offset I_CLIENT_PFn__I_MSIX_PENDING_​INTRPT__PBAO EP 0x0 - 0x1fffffff
MSI-X Table Offset I_CLIENT_PFn__I_MSIX_TBL_​OFFSET__TO EP 0x0 - 0x1fffffff
MSI-X Table Size I_CLIENT_PFn__I_MSIX_CTRL__​MSIXTS EP 0x0 - 0x7ff
Programming Interface Byte I_CLIENT_PFn__I_REVISION_​ID_CLASS_CODE__PIB EP 0x0 - 0xff
Resizable BAR Enable I_CLIENT_LM__I_PF_n_BAR_​CONFIG_1_REG__ERBC EP 0, 1
Revision ID I_CLIENT_PFn__I_REVISION_​ID_CLASS_CODE__RID EP 0x0 - 0xff
Sub-Class Code I_CLIENT_PFn__I_REVISION_​ID_CLASS_CODE__SCC EP 0x0 - 0xff
Subsystem ID I_CLIENT_PFn__I_SUBSYSTEM_​VENDOR_ID_SUBSYSTEM_I__SID EP 0x0 - 0xffff
User ID register from Vendor Specific Extended Capability I_CLIENT_PFn__I_VENDOR_​SPECIFIC_HEADER_REG__VI EP 0x0 - 0xffff
Table 6. Physical Function n - Virtual Function
GUI Name API Name Mode Values
ATS Enable SS_PCIE_PFn_VF_ATS_EN EP 0, 1
Enable TPH SS_PCIE_PFn_VF_TPH_EN EP 0, 1
MSI Multiple Message Capable SS_PCIE_PFn_VF_MSI_MUL_​MESSAGE_CAP EP 1, 2, 4, 8, 16, 32
MSI-X BAR Indicator SS_PCIE_PFn_VF_MSIX_BAR_IND EP 'BAR0', 'BAR1', 'BAR2', 'BAR3', 'BAR4', 'BAR5'
MSI-X PBA Indicator SS_PCIE_PFn_VF_MSIX_PBA_IND EP 'BAR0', 'BAR1', 'BAR2', 'BAR3', 'BAR4', 'BAR5'
MSI-X PBA Offset SS_PCIE_PFn_VF_MSIX_PBA_OFFSET EP 0x0 - 0x1fffffff
MSI-X Table Offset SS_PCIE_PFn_VF_MSIX_TABLE_OFFSET EP 0x0 - 0x1fffffff
MSI-X Table Size SS_PCIE_PFn_VF_MSIX_TABLE_SIZE EP 0x0 - 0x7ff
Steering Tag Table Location SS_PCIE_PFn_VF_STEERING_​TAG_TAB_LOC EP 'ST Table in the TPH Requester Capability Structure', 'ST Table not present', 'ST values stored in the MSI-X Table in client RAM'
Steering Tag Table Size SS_PCIE_PFn_VF_STEERING_​TAG_TAB_SIZE EP 0 - 2047
Subsystem ID SS_PCIE_PFn_VF_SUBSYSTEM_ID EP 0x0 - 0xffff
VF BAR0 Aperture I_CLIENT_LM__I_PF_n_VF_BAR_​CONFIG_0_REG__VFBAR0A EP '1 GB', '1 KB', '1 MB', '128 B', '128 GB', '128 KB', '128 MB', '16 GB', '16 KB', '16 MB', '2 GB', '2 KB', '2 MB', '256 B', '256 GB', '256 KB', '256 MB', '32 GB', '32 KB', '32 MB', '4 GB', '4 KB', '4 MB', '512 B', '512 KB', '512 MB', '64 GB', '64 KB', '64 MB', '8 GB', '8 KB', '8 MB'
VF BAR0 Control I_CLIENT_LM__I_PF_n_VF_BAR_​CONFIG_0_REG__VFBAR0C EP '32 bit I/O BAR', '32 bit non-prefetchable memory BAR', '32 bit prefetchable memory BAR', '64 bit non-prefetchable memory BAR', '64 bit prefetchable memory BAR', 'Disabled'
VF BAR1 Aperture I_CLIENT_LM__I_PF_n_VF_BAR_​CONFIG_0_REG__VFBAR1A EP '1 GB', '1 KB', '1 MB', '128 B', '128 KB', '128 MB', '16 KB', '16 MB', '2 GB', '2 KB', '2 MB', '256 B', '256 KB', '256 MB', '32 KB', '32 MB', '4 KB', '4 MB', '512 B', '512 KB', '512 MB', '64 KB', '64 MB', '8 KB', '8 MB'
VF BAR1 Control I_CLIENT_LM__I_PF_n_VF_BAR_​CONFIG_0_REG__VFBAR1C EP '32 bit I/O BAR', '32 bit non-prefetchable memory BAR', '32 bit prefetchable memory BAR', 'Disabled'
VF BAR2 Aperture I_CLIENT_LM__I_PF_n_VF_BAR_​CONFIG_0_REG__VFBAR2A EP '1 GB', '1 KB', '1 MB', '128 B', '128 GB', '128 KB', '128 MB', '16 GB', '16 KB', '16 MB', '2 GB', '2 KB', '2 MB', '256 B', '256 GB', '256 KB', '256 MB', '32 GB', '32 KB', '32 MB', '4 GB', '4 KB', '4 MB', '512 B', '512 KB', '512 MB', '64 GB', '64 KB', '64 MB', '8 GB', '8 KB', '8 MB'
VF BAR2 Control I_CLIENT_LM__I_PF_n_VF_BAR_​CONFIG_0_REG__VFBAR2C EP '32 bit I/O BAR', '32 bit non-prefetchable memory BAR', '32 bit prefetchable memory BAR', '64 bit non-prefetchable memory BAR', '64 bit prefetchable memory BAR', 'Disabled'
VF BAR3 Aperture I_CLIENT_LM__I_PF_n_VF_BAR_​CONFIG_0_REG__VFBAR3A EP '1 GB', '1 KB', '1 MB', '128 B', '128 KB', '128 MB', '16 KB', '16 MB', '2 GB', '2 KB', '2 MB', '256 B', '256 KB', '256 MB', '32 KB', '32 MB', '4 KB', '4 MB', '512 B', '512 KB', '512 MB', '64 KB', '64 MB', '8 KB', '8 MB'
VF BAR3 Control I_CLIENT_LM__I_PF_n_VF_BAR_​CONFIG_0_REG__VFBAR3C EP '32 bit I/O BAR', '32 bit non-prefetchable memory BAR', '32 bit prefetchable memory BAR', 'Disabled'
VF BAR4 Aperture I_CLIENT_LM__I_PF_n_VF_BAR_​CONFIG_1_REG__VFBAR4A EP '1 GB', '1 KB', '1 MB', '128 B', '128 GB', '128 KB', '128 MB', '16 GB', '16 KB', '16 MB', '2 GB', '2 KB', '2 MB', '256 B', '256 GB', '256 KB', '256 MB', '32 GB', '32 KB', '32 MB', '4 GB', '4 KB', '4 MB', '512 B', '512 KB', '512 MB', '64 GB', '64 KB', '64 MB', '8 GB', '8 KB', '8 MB'
VF BAR4 Control I_CLIENT_LM__I_PF_n_VF_BAR_​CONFIG_1_REG__VFBAR4C EP '32 bit I/O BAR', '32 bit non-prefetchable memory BAR', '32 bit prefetchable memory BAR', '64 bit non-prefetchable memory BAR', '64 bit prefetchable memory BAR', 'Disabled'
VF BAR5 Aperture I_CLIENT_LM__I_PF_n_VF_BAR_​CONFIG_1_REG__VFBAR5A EP '1 GB', '1 KB', '1 MB', '128 B', '128 KB', '128 MB', '16 KB', '16 MB', '2 GB', '2 KB', '2 MB', '256 B', '256 KB', '256 MB', '32 KB', '32 MB', '4 KB', '4 MB', '512 B', '512 KB', '512 MB', '64 KB', '64 MB', '8 KB', '8 MB'
VF BAR5 Control I_CLIENT_LM__I_PF_n_VF_BAR_​CONFIG_1_REG__VFBAR5C EP '32 bit I/O BAR', '32 bit non-prefetchable memory BAR', '32 bit prefetchable memory BAR', 'Disabled'
Table 7. BAR0 Address Translation
GUI Name API Name Mode Values
Number of PCIe address bits to pass through (actual bits - 1) SS_PCIE_INBOUND_RC_BAR0_PCIE_NUM_BITS RP 8 - 64
AXI address 63:8 SS_PCIE_INBOUND_RC_BAR0_ADDR RP 0x0 - 0xffffffffffffff
Table 8. BAR1 Address Translation
GUI Name API Name Mode Values
Number of PCIe address bits to pass through (actual bits - 1) SS_PCIE_INBOUND_RC_BAR1_PCIE_NUM_BITS RP 8 - 64
AXI address 63:8 SS_PCIE_INBOUND_RC_BAR1_ADDR RP 0x0 - 0xffffffffffffff
Table 9. RP Outbound
GUI Name API Name Mode Values
Regional Configurations file RP_OUTBOUND_FILENAME All Filename (.json)
Table 10. Device Capability
GUI Name API Name Mode Values
Device Serial Number (DW1) I_CLIENT_PF0__I_DEV_SER_NUM_0__DSND0 EP 0x0 - 0xffffffff
Device Serial Number (DW1) I_CLIENT_RC__I_DEV_SER_NUM_0__DSND0 RP 0x0 - 0xffffffff
Device Serial Number (DW2) I_CLIENT_PF0__I_DEV_SER_NUM_1__DSND1 EP 0x0 - 0xffffffff
Device Serial Number (DW2) I_CLIENT_RC__I_DEV_SER_NUM_1__DSND1 RP 0x0 - 0xffffffff
Enable Slot Clock Configuration I_CLIENT_PF0__I_LINK_CTRL_STATUS__SCC EP 0, 1
Enable Slot Clock Configuration I_CLIENT_RC__I_LINK_CTRL_STATUS__SCC RP 0, 1
Extended Tag Field I_CLIENT_PF0__I_PCIE_DEV_CTRL_STATUS__ETFE EP 0, 1
Extended Tag Field I_CLIENT_RC__I_PCIE_DEV_CTRL_STATUS__ETE RP 0, 1
Link Port Number I_CLIENT_RC__I_LINK_CAP__PN RP 0 - 255
Table 11. Slot Capability
GUI Name API Name Mode Values
Attention Button Pressed Enable I_CLIENT_RC__I_SLOT_CAPABILITY__ABPRSNT RP 0, 1
Power Controller Present I_CLIENT_RC__I_SLOT_CAPABILITY__PCP RP 0, 1
Power Controller Control I_CLIENT_RC__I_SLOT_CTRL_STATUS__PCC RP 'Power Off', 'Power On'
Power Fault Detected Enable I_CLIENT_RC__I_SLOT_CTRL_STATUS__PFDE RP 0, 1
MRL Sensor Changed Enable I_CLIENT_RC__I_SLOT_CAPABILITY__MRLSP RP 0, 1
Attention Indicator Enable I_CLIENT_RC__I_SLOT_CAPABILITY__AIP RP 0, 1
Attention Indicator Control I_CLIENT_RC__I_SLOT_CTRL_STATUS__AIC RP 'Blink', 'Off', 'On'
Power Indicator Enable I_CLIENT_RC__I_SLOT_CAPABILITY__PIP RP 0, 1
Power Indicator Control I_CLIENT_RC__I_SLOT_CTRL_STATUS__PIC RP 'Blink', 'Off', 'On'
Electromechanical Interlock Enable I_CLIENT_RC__I_SLOT_CAPABILITY__EIP RP 0, 1
Hot-plug Capable I_CLIENT_RC__I_SLOT_CAPABILITY__HPC RP 0, 1
Presence Detect Changed Enable I_CLIENT_RC__I_SLOT_CTRL_STATUS__PDCE RP 0, 1
Command Completed Interrupt Enable SS_PCIE_SLOT_CAPABILITY_CCIE RP 0, 1
Hot-plug Surprise I_CLIENT_RC__I_SLOT_CAPABILITY__HPS RP 0, 1
Slot Power Limit Scale I_CLIENT_RC__I_SLOT_CAPABILITY__SPLS RP '0.001x', '0.01x', '0.1x', '1.0x'
Slot Power Limit Value I_CLIENT_RC__I_SLOT_CAPABILITY__SPLV RP 0 - 255
Slot Number I_CLIENT_RC__I_SLOT_CAPABILITY__PSN RP 0 - 8191
Table 12. AXI
GUI Name API Name Mode Values
Enable AXI Master Interface AXI_MASTER_EN All 0, 1
Enable AXI Slave Interface AXI_SLAVE_EN All 0, 1
AXI Clock Pin Name AXI_CLK_PIN All Pin name
Invert AXI Clock Pin AXI_CLK_INVERT_EN All 0 - 1
AXI Reset (Active-Low) Pin Name USER_AXI_RESET_N_PIN All Pin name
Table 13. AXI Master/Slave Read Address Channel
GUI Name API Name Mode Values
Address ID 7:0 Bus Name <TARGET/MASTER>_AXI_ARID_PIN All Pin name
Address Ready Pin Name <TARGET/MASTER>_AXI_ARREADY_PIN All Pin name
Address Valid Pin Name <TARGET/MASTER>_AXI_ARVALID_PIN All Pin name
Burst Length 7:0 Bus Name <TARGET/MASTER>_AXI_ARLEN_PIN All Pin name
Burst Size 2:0 Bus Name <TARGET/MASTER>_AXI_ARSIZE_PIN All Pin name
Read Address User 87:0 Bus Name <TARGET/MASTER>_AXI_ARUSER_PIN All Pin name
Read Address 63:0 Bus Name <TARGET/MASTER>_AXI_ARADDR_PIN All Pin name
Table 14. AXI Master/Slave Write Address Channel
GUI Name API Name Mode Values
Address ID 7:0 Bus Name <TARGET/MASTER>_AXI_AWID_PIN All Pin name
Address Ready Pin Name <TARGET/MASTER>_AXI_AWREADY_PIN All Pin name
Address Valid Pin Name <TARGET/MASTER>_AXI_AWVALID_PIN All Pin name
Burst Length 7:0 Bus Name <TARGET/MASTER>_AXI_AWLEN_PIN All Pin name
Burst Size 2:0 Bus Name <TARGET/MASTER>_AXI_AWSIZE_PIN All Pin name
Write Address User 87:0 Bus Name <TARGET/MASTER>_AXI_AWUSER_PIN All Pin name
Write Address 63:0 Bus Name <TARGET/MASTER>_AXI_AWADDR_PIN All Pin name
Table 15. AXI Master/Slave Write Response Channel
GUI Name API Name Mode Values
Response ID Tag Parity Pin Name <TARGET/MASTER>_AXI_BID_PAR_PIN All Pin name
Response ID Tag 7:0 Bus Name <TARGET/MASTER>_AXI_BID_PIN All Pin name
Response Ready Pin Name <TARGET/MASTER>_AXI_BREADY_PIN All Pin name
Write Response Parity Pin Name <TARGET/MASTER>_AXI_BRESP_PAR_PIN All Pin name
Write Response Valid Pin Name <TARGET/MASTER>_AXI_BVALID_PIN All Pin name
Write Response 1:0 Bus Name <TARGET/MASTER>_AXI_BRESP_PIN All Pin name
Table 16. AXI Master/Slave Read Data Channel
GUI Name API Name Mode Values
Read Data Parity 31:0 Bus Name <TARGET/MASTER>_AXI_RDATA_PAR_PIN All Pin name
Read Data 255:0 Bus Name <TARGET/MASTER>_AXI_RDATA_PIN All Pin name
Read ID Tag Parity Pin Name <TARGET/MASTER>_AXI_RID_PAR_PIN All Pin name
Read ID Tag 7:0 Bus Name <TARGET/MASTER>_AXI_RID_PIN All Pin name
Read Last Pin Name <TARGET/MASTER>_AXI_RLAST_PIN All Pin name
Read Ready Pin Name <TARGET/MASTER>_AXI_RREADY_PIN All Pin name
Read Response Parity Pin Name <TARGET/MASTER>_AXI_RRESP_PAR_PIN All Pin name
Read Response 1:0 Bus Name <TARGET/MASTER>_AXI_RRESP_PIN All Pin name
Read Valid Pin Name <TARGET/MASTER>_AXI_RVALID_PIN All Pin name
Table 17. AXI Master/Slave Write Data Channel
GUI Name API Name Mode Values
Address Ready Pin Name <TARGET/MASTER>_AXI_WREADY_PIN All Pin name
Write Data Parity 31:0 Bus Name <TARGET/MASTER>_AXI_WDATA_PAR_PIN All Pin name
Write Data 255:0 Bus Name <TARGET/MASTER>_AXI_WDATA_PIN All Pin name
Write Last Pin Name <TARGET/MASTER>_AXI_WLAST_PIN All Pin name
Write Strobes Parity 3:0 Bus Name <TARGET/MASTER>_AXI_WSTRB_PAR_PIN All Pin name
Write Strobes 31:0 Bus Name <TARGET/MASTER>_AXI_WSTRB_PIN All Pin name
Write Valid Pin Name <TARGET/MASTER>_AXI_WVALID_PIN All Pin name
Table 18. AXI Master Sideband
GUI Name API Name Mode Values
Non-Posted TLP Pin Name TARGET_NON_POSTED_REJ_PIN All Pin name
Table 19. Interrupt
GUI Name API Name Mode Values
Enable Interrupt INTERRUPT_EN All 0, 1
Interrupt Sideband Signals 27:0 Bus Name INTERRUPT_SIDEBAND_SIGNALS_PIN All Pin name
Local Error and Status Register Interrupt Pin Name LOCAL_INTERRUPT_PIN All Pin name
Table 20. Legacy Interrupt
GUI Name API Name Mode Values
INTA Output Pin Name INTA_OUT_PIN RP Pin name
INTB Output Pin Name INTB_OUT_PIN RP Pin name
INTC Output Pin Name INTC_OUT_PIN RP Pin name
INTD Output Pin Name INTD_OUT_PIN RP Pin name
INTx Acknowledge Pin Name INT_ACK_PIN EP Pin name
Interrupt Input A Pin Name INTA_IN_PIN EP Pin name
Interrupt Input B Pin Name INTB_IN_PIN EP Pin name
Interrupt Input C Pin Name INTC_IN_PIN EP Pin name
Interrupt Input D Pin Name INTD_IN_PIN EP Pin name
Interrupt Pending Status 3:0 Bus Name INT_PENDING_STATUS_PIN EP Pin name
Table 21. MSI
GUI Name API Name Mode Values
Enable MSI MSI_EN EP 0, 1
PF0 MSI Pending Status Input 31:0 Bus Name PF0_MSI_PENDING_STATUS_IN_PIN EP Pin name
PF1 MSI Pending Status Input 31:0 Bus Name PF1_MSI_PENDING_STATUS_IN_PIN EP Pin name
PF2 MSI Pending Status Input 31:0 Bus Name PF2_MSI_PENDING_STATUS_IN_PIN EP Pin name
PF3 MSI Pending Status Input 31:0 Bus Name PF3_MSI_PENDING_STATUS_IN_PIN EP Pin name
Table 22. Message
GUI Name API Name Mode Values
Message Byte Enable 31:0 Bus Name MSG_BYTE_EN_PIN All Pin name
Message Data Indication Pin Name MSG_DATA_PIN All Pin name
Message End Pin Name MSG_END_PIN All Pin name
Message PASID Present Pin Name MSG_PASID_PRESENT_PIN All Pin name
Message PASID 21:0 Bus Name MSG_PASID_PIN All Pin name
Message Start Pin Name MSG_START_PIN All Pin name
Message Valid Pin Name MSG_VALID_PIN All Pin name
Message Vendor Defined Header Pin Name MSG_VDH_PIN All Pin name
Message 255:0 Bus Name MSG_PIN All Pin name
Table 23. Error Indicator
GUI Name API Name Mode Values
Correctable Error Input Pin Name CORRECTABLE_ERROR_IN_PIN All Pin name
Correctable Error Output Pin Name CORRECTABLE_ERROR_OUT_PIN All Pin name
Fatal Error Output Pin Name FATAL_ERROR_OUT_PIN All Pin name
Non-Fatal Error Output Pin Name NON_FATAL_ERROR_OUT_PIN All Pin name
PHY Interrupt Output Pin Name PHY_INTERRUPT_OUT_PIN RP Pin name
Uncorrectable Error Input Pin Name UNCORRECTABLE_ERROR_IN_PIN All Pin name
Table 24. APB
GUI Name API Name Mode Values
APB Interface Clock Pin Name USER_APB_CLK_PIN All Pin name
Invert APB Interface Clock Pin USER_APB_CLK_INVERT_EN All 0:1
APB Address 23:0 Bus Name USER_APB_PADDR_PIN All Pin name
APB Enable Pin Name USER_APB_PENABLE_PIN All Pin name
APB Read Data Parity 3:0 Bus Name USER_APB_PRDATA_PAR_PIN All Pin name
APB Read Data 31:0 Bus Name USER_APB_PRDATA_PIN All Pin name
APB Ready Pin Name USER_APB_PREADY_PIN All Pin name
APB Select Pin Name USER_APB_PSEL_PIN All Pin name
APB Strobe Parity Pin Name USER_APB_PSTRB_PAR_PIN All Pin name
APB Strobe 3:0 Bus Name USER_APB_PSTRB_PIN All Pin name
APB Write Data Parity 3:0 Bus Name USER_APB_PWDATA_PAR_PIN All Pin name
APB Write Data 31:0 Bus Name USER_APB_PWDATA_PIN All Pin name
APB Write/Read Access Pin Name USER_APB_PWRITE_PIN All Pin name
Table 25. Hot Plug
GUI Name API Name Mode Values
Adapter Presence (Active-Low) Pin Name PRSNT_N_PIN RP Pin name
Attention Button (Active-Low) Pin Name ATTENTION_BUTTON_N_PIN RP Pin name
Attention Indicator Control Output 1:0 Bus Name ATTN_INDICATOR_PIN RP Pin name
Command Changed Pin Name COMMAND_CHANGED_PIN RP Pin name
Command Completed Pin Name COMMAND_COMPLETED_PIN RP Pin name
Electromechanical Interlock (EMI) Control Pin Name EMI_CTRL_PIN RP Pin name
Electromechanical Interlock (EMI) Pin Name EMI_STATUS_PIN RP Pin name
Hot Plug Interrupt Pin Name HOT_PLUG_INTERRUPT_OUT_PIN RP Pin name
Manually-operated Retention Latch (Active-Low) Pin Name MRL_SENSOR_N_PIN RP Pin name
Power Control Pin Name PWR_CTRL_PIN RP Pin name
Power Fault (Active-Low) Pin Name POWER_FAULT_N_PIN RP Pin name
Power Indicator Control Output 1:0 Bus Name PWR_INDICATOR_PIN RP Pin name
Table 26. Function-Level Reset
GUI Name API Name Mode Values
FLR In Progress 3:0 Bus Name FLR_IN_PROGRESS_PIN EP Pin name
Function Level Reset (FLR) Done 3:0 Bus Name FLR_DONE_PIN EP Pin name
VF FLR In Progress 63:0 Bus Name VF_FLR_IN_PROGRESS_PIN EP Pin name
Virtual Function FLR Done 63:0 Bus Name VF_FLR_DONE_PIN EP Pin name
Table 27. Status
GUI Name API Name Mode Values
Enable Status STATUS_EN All 0, 1
APB Access Clock Shutoff Pin Name REG_ACCESS_CLK_SHUTOFF_PIN All Pin name
Core Clock Shutoff Pin Name CORE_CLK_SHUTOFF_PIN All Pin name
Function Status 15:0 Bus Name FUNCTION_STATUS_PIN All Pin name
LTSSM State 5:0 Bus Name LTSSM_STATE_PIN All Pin name
PCIe Link Status 1:0 Bus Name LINK_STATUS_PIN All Pin name
PCIe Maximum Payload Size 2:0 Bus Name PCIE_MAX_PAYLOAD_SIZE_PIN All Pin name
PCIe Maximum Read Request Size 2:0 Bus Name PCIE_MAX_READ_REQ_SIZE_PIN All Pin name
PIPE P00 Rate 1:0 Bus Name PIPE_P00_RATE_PIN All Pin name
Ready Pin Name PMA_CMN_READY_PIN All Pin name
Table 28. Configuration Snoop
GUI Name API Name Mode Values
Enable Configuration Snoop CFG_SNOOP_EN All 0, 1
Configuration Function Number 7:0 Bus Name CONFIG_FUNCTION_NUM_PIN All Pin name
Configuration Read Data Parity 3:0 Bus Name CONFIG_READ_DATA_PAR_PIN All Pin name
Configuration Read Data Valid Pin Name CONFIG_READ_DATA_VALID_PIN All Pin name
Configuration Read Data 31:0 Bus Name CONFIG_READ_DATA_PIN All Pin name
Configuration Read Received Pin Name CONFIG_READ_RECEIVED_PIN All Pin name
Configuration Register Address 9:0 Bus Name CONFIG_REG_NUM_PIN All Pin name
Configuration Write Byte Enable Parity Pin Name CONFIG_WRITE_BYTE_ENABLE_PAR_PIN All Pin name
Configuration Write Byte Enable 3:0 Bus Name CONFIG_WRITE_BYTE_ENABLE_PIN All Pin name
Configuration Write Data Parity 3:0 Bus Name CONFIG_WRITE_DATA_PAR_PIN All Pin name
Configuration Write Data 31:0 Bus Name CONFIG_WRITE_DATA_PIN All Pin name
Configuration Write Received Pin Name CONFIG_WRITE_RECEIVED_PIN All Pin name
Table 29. Power Management
GUI Name API Name Mode Values
Enable Power Management PWR_MGMT_EN All 0, 1
ASPM Enable SS_PCIE_ASPM EP 'Disabled', 'L0s Entry', 'L0s and L1 Entry', 'L1 Entry'
ASPM L1.1 Substate Enable I_CLIENT_PF0__I_L1_PM_CTRL_1__​L1ASPML11EN EP 0, 1
ASPM L1.2 Substate Enable I_CLIENT_PF0__I_L1_PM_CTRL_1__​L1ASPML12EN EP 0, 1
PM L1.1 Substate Enable I_CLIENT_PF0__I_L1_PM_CTRL_1__​L1PML11EN EP 0, 1
PM L1.2 Substate Enable I_CLIENT_PF0__I_L1_PM_CTRL_1__​L1PML12EN EP 0, 1
ASPM Enable I_CLIENT_RC__I_LINK_CTRL_STATUS__​ASPMC RP 'Disabled', 'L0s Entry', 'L0s and L1 Entry', 'L1 Entry'
ASPM L1.1 Substate Enable I_CLIENT_RC__I_L1_PM_CTRL_1__​L1ASPML11EN RP 0, 1
ASPM L1.2 Substate Enable I_CLIENT_RC__I_L1_PM_CTRL_1__​L1ASPML12EN RP 0, 1
PM L1.1 Substate Enable I_CLIENT_RC__I_L1_PM_CTRL_1__​L1PML11EN RP 0, 1
PM L1.2 Substate Enable I_CLIENT_RC__I_L1_PM_CTRL_1__​L1PML12EN RP 0, 1
Port Common Mode Restore Time (us) I_CLIENT_PF0__I_L1_PM_CAP__​L1PRTCMMDRESTRTIME EP 0 - 255
Port Power On Time Scale I_CLIENT_PF0__I_L1_PM_CAP__​L1PRTPVRONSCALE EP '100us', '10us', '2us'
Port Power On Time Value I_CLIENT_PF0__I_L1_PM_CAP__R0 EP 0 - 3'
Port Common Mode Restore Time (us) I_CLIENT_RC__I_L1_PM_CAP__​L1PRTCMMDRESTRTIME RP 0 - 255
Port Power On Time Scale I_CLIENT_RC__I_L1_PM_CAP__​L1PRTPVRONSCALE RP '100us', '10us', '2us'
Port Power On Time Value I_CLIENT_RC__I_L1_PM_CAP__R0 RP 0 - 31
Power Management Clock Pin Name PM_CLK_PIN All Pin name
Power Management Clock Connection Type PMCLK_CONN_TYPE All 'gclk', 'rclk'
Dynamic Power Allocation Interrupt 3:0 Bus Name DPA_INTERRUPT_PIN EP Pin name
L1 Exit Request Pin Name CLIENT_REQ_EXIT_L1_PIN All Pin name
PCIe Link Power State 3:0 Bus Name PCIE_LINK_POWER_STATE_PIN All Pin name
Power State Change Acknowledge Pin Name POWER_STATE_CHANGE_ACK_PIN All Pin name
Power State Change Function 7:0 Bus Name POWER_STATE_CHANGE_​FUNCTION_NUM_PIN All Pin name
Power State Change Interrupt Pin Name POWER_STATE_CHANGE_​INTERRUPT_PIN All Pin name
Power State Function 11:0 Bus Name FUNCTION_POWER_STATE_PIN All Pin name
Transition PM to L23_READY Request Pin Name REQ_PM_TRANSITION_L23_READY_PIN EP Pin name
Table 30. L1 Substate
GUI Name API Name Mode Values
Clock Request Input (Active-Low) Pin Name CLKREQ_IN_N_PIN All Pin name
Clock Request Output (Active-Low) Pin Name CLKREQ_OUT_N_PIN All Pin name
L1 PM Substate 2:0 Bus Name L1_PM_SUBSTATE_OUT_PIN All Pin name
L1-Substate Exit Request Pin Name CLIENT_REQ_EXIT_L1_SUBSTATE_PIN All Pin name
Table 31. Vendor Specific
GUI Name API Name Mode Values
Enable Vendor Specific VENDOR_EN EP 0, 1
PF0 Control Input 7:0 Bus Name F0_VSEC_CONTROL_IN_PIN EP Pin name
PF0 Interrupt Output Pin Name F0_VSEC_INTERRUPT_OUT_PIN EP Pin name
PF1 Control Input7:0 Bus Name F1_VSEC_CONTROL_IN_PIN EP Pin name
PF1 Interrupt Output Pin Name F1_VSEC_INTERRUPT_OUT_PIN EP Pin name
PF2 Control Input 7:0 Bus Name F2_VSEC_CONTROL_IN_PIN EP Pin name
PF2 Interrupt Output Pin Name F2_VSEC_INTERRUPT_OUT_PIN EP Pin name
PF3 Control Input 7:0 Bus Name F3_VSEC_CONTROL_IN_PIN EP Pin name
PF3 Interrupt Output Pin Name F3_VSEC_INTERRUPT_OUT_PIN EP Pin name