SPI Flash Property Reference

All of these SPI flash block properties are applicable to Titanium FPGAs in F100S3F2 packages and Trion FPGAs in QFP100F3 packages only.

Table 1. SPI Flash Properties
API Name GUI Name Values
CLK_PIN Clock Pin Name Pin name
CS_N_OE_PIN Flash Chip Select (Active-Low) Output Enable Pin Name Pin name
CS_N_OUT_PIN Flash Chip Select (Active-Low) Pin Name Pin name
HOLD_N_IN_PIN Hold (Active-Low) Input Pin Name Pin name
HOLD_N_OE_PIN Hold (Active-Low) Output Enable Pin Name Pin name
HOLD_N_OUT_PIN Hold (Active-Low) Pin Name Pin name
MISO_IN_PIN Data Input From Flash Pin Name Pin name
MISO_OE_PIN Data Input From Flash Output Enable Pin Name Pin name
MISO_OUT_PIN Data Input From Flash Output Pin Name Pin name
MOSI_IN_PIN Data Output To Flash Input Pin Name Pin name
MOSI_OUT_PIN Data Output To Flash Pin Name Pin name
MOSI_OE_PIN Data Output To Flash Output Enable Pin Name Pin name
MULT_CTRL_EN Enable Multiple Controller 0, 1
NAME Instance Name Instance Name
RESOURCE SPI Flash Resource SPI_FLASH0
REG_EN Enable Register Interface 0, 1
RW_WIDTH Read/Write Width x1, x2, x4
SCLK_OE_PIN Clock Output to Flash Output Enable Pin Name Pin name
SCLK_OUT_PIN Clock Output to Flash Pin Name Pin name
WP_N_OE_PIN Write Protect (Active-Low) Output Enable Pin Name Pin name
WP_N_IN_PIN Write Protect (Active-Low) Input Pin Name Pin name
WP_N_OUT_PIN Write Protect (Active-Low) Pin Name Pin name
Table 2. Deprecated SPI Flash Properties
API Name Deprecated In Replacement
CS_N_PIN 2023.1 CS_N_OUT_PIN
ENA_OE 2023.1 MULT_CTRL_EN
HOLD_N_PIN 2023.1 HOLD_N_OUT_PIN
MISO_PIN 2023.1 MISO_IN_PIN
MOSI_PIN 2023.1 MOSI_OUT_PIN
SCLK_PIN 2023.1 SCLK_OUT_PIN
WP_N_PIN 2023.1 WP_N_OUT_PIN