Specifying Language Support

You can set the language support at the project level or at the file level. In both cases, you make this setting in the Design tab of the Project Editor dialog box. Open the Project Editor by choosing File > Edit Project or by clicking the toolbar button.

Verilog HDL Choices VHDL Choices
verilog_2k vhdl_2008
verilog_95 vhdl_1993
SystemVerilog2005
SystemVerilog2009