Concurrent Debugging

In the Efinity software v2025.2 or higher, has an improved concurrent debugging mode (this improved mode does not require you to set up a hardware server). Concurrent debugging let you use the RISC-V IDE and multiple Efinity debuggers concurrently with a single FTDI interface.

When you enable concurrent debugging mode, OpenOCD is used as the JTAG back end. The Efinity software launches a daemon to manage the life cycle of OpenOCD processes automatically.

Note: The legacy concurrent debugger using the Efinity Hardware Server is no longer maintained as of the Efinity software v2025.2.
Concurrent debugging supports the following tools:
  • Logic Analyzer
  • Virtual I/O
  • Transceiver Debugger
  • RISC-V IDE
  • Standalone Efinity Programmer
Concurrent debugging does not support the following tools and FPGAs:
  • All Trion T4, T8, and T13 FPGAs
  • Trion T20W80, T20Q100, T2Q144, T20F169, and T20F256 FPGAs
  • Efinity SVF Player
  • SPI Active programming mode
To use concurrent debugging:
  1. Use the Debugger to create debug cores. Connect the debug cores and RISC-V SoCs to different JTAG User TAP interfaces (e.g., USER1 and USER2).
  2. Compile the project.
  3. Open Debugger windows for each JTAG User TAP interface. To open more than one Debugger window, choose Tools > Open Debugger or click the Debugger icon multiple times.
  4. Turn on the Shared option in the Debugger or Transceiver Debugger window to enable concurrent debugging mode.
  5. Start debugging.
Notice: For more information on using RISC-V SoCs, see the Sapphire RISC-V SoC Hardware and Software User Guide.