Revision History

Updated PCIe Property Reference to include root port properties. (DOC-2832)

Added WRITEBUFFER_SOC_AXI_​INTERFACE_EN property. (DOC-2740)

Added core reference clock properties. (DOC-2741)

Added PMA Direct parameters. (DOC-2590)

Updated value for REMOTE_UPDATE_RETRIES property. (DOC-2614)

Updated Table 1, Table 2, and Table 11. (DOC-2559)

Updated HyperRAM Property Reference. (DOC-2571)

Added auto_calc_quad_clock() command. Added Custom choice for PMA Direct MODE parameter. (DOC-2576)

Added support for XGMII, SGMII, and PMA Direct mixed protocols. (DOC-2471)

Added support for PCIe compliance mode. (DOC-2490)

Added new API command: get_block_version(). (DOC-2509)

Added new API command: get_all_block_version(). (DOC-2509)

Changed "MSIX" to "MSI-X (master)" in PCIe Property Reference.

Added 'Tx FIFO' to PCIe Property Reference.

Added SoC property to enable the pipeline path. (DOC-2283)

10GBase-KR interface renamed as Ethernet XGMII.

The create_block function includes the cmn_name argument for PMA Direct, Ethernet XGMII, and Ethernet SGMII. (DOC-2274)

Updated PMA Direct preset options. (DOC-2270)

Added PCI Express properties for MSIX Capability ID and MSIX Capabilities Pointer. (DOC-2294)

Added PMA Direct Common: Clock and Reset properties. (DOC-2224)

Added more preset optios for PMA Direct PRESET property. (DOC-2237)

Renamed PMA Direct property SW_RAW_REFCLK_FREQ as SS_RAW_REFCLK_FREQ and added more clock frequencies. (DOC-2237)

Added support for Topaz family.

Updated Physical Function blocks and properties in PCIe topic. (DOC-2158)

Updated get_all_preset_info(), get_preset(), and set_preset() API functions for PMA Direct. (DOC-2044)

Updated PCIe properties for power management and interrupt pins. (DOC-2000)

Enable KR Base property moved to Control Properties table. (DOC-2026)

Added QUAD_PCIE and 10GBASE_KR blocks and properties.

DDR CLK_NAME, CLK_RESOURCE, and CLK_PIN properties are read-only, and add a new property CLKIN_SEL. (DOC-1916)

Added functions to get and set I/O bank mode select pins; added function to get the bonded I/O bank name. (DOC-1729)

Added CLKOUTn_PHASE_STEP PLL property. (DOC-1897)

Added result_len argument to auto_calc_pll_clock(). (DOC-1537)

Added reset_device_settings() and clear design API functions. (DOC-1558)

Added Pin Swizzling property for DDR. (DOC-1470)

Added DBI_READ_EN and DBI_WRITE_EN properties for Titanium DDR block. (DOC-1276)

Added Output Clock Inversion property which allows the inversion of output clock individually. (DOC-941)

Updated SPI Flash block properties and added support for Trion FPGAs in QFP100F3 packages. (DOC-1297)

Added PLL SSC block and updated MIPI DPHY PLL SSC properties. (DOC-1297)

Added note about deprecated properties.

Updated Titanium DDR block AXI Width property. (DOC-1209)

Updated auto_calc_pll_clock() function for PLL V3. (DOC-1193)

Added clock multiplexer specific API commands.

Updated for Efinity® v2022.1

Removed support for GCTRL in Titanium and removed support for PLL_EXTFB in Trion. (DOC-849)

Added more get and set functions.

Added remote update, SEU, HyperRAM, SPI flash, MIPI DPHY property references. Updated LVDS, PLL property references.

Added API functions and property settings for I/O banks.

Updated PLL properties for Titanium Ti90, Ti120, and Ti180 FPGAs.

Corrected the API functions for obtaining version information. The top-level class is APIVersion. (DOC-521)

Added support for Titanium family.

Added table of exceptions.

Added table of API packages.

Renamed document as Efinity Python API.

Updated for Efinity® v2020.2

Added PLL properties table.

Updated the block types supported in v2020.2

Clarified usage for create_block() and set_property(). (DOC-279)

Added IN_REG, OUT_REG, and OE_REG GPIO properties. (DOC-279)

Added the create_vref_gpio() function.