Sequential Optimization
Sequential optimization simplifies a circuit with registers by finding and merging signals that are logically equivalent over time. To deduce sequentially equivalent logic, the algorithm performs logic partitioning, fast simulation, and other proofing techniques. The following is an example of sequential equivalent logic:
// Two 3-bit counters with different encodings
Counter_A: 000 → 001 → 010 → 011 → 100 → 101 → 110 → 111 → 000...
Counter_B: 001 → 000 → 011 → 010 → 101 → 100 → 111 → 110 → 001...Counters A and B, which depend on the same inputs and clock signal, have the same
transition behavior, except that counter B's bit 0 is a logical inversion of
counter A. After sequential optimization, the two counters are
merged:
Counter_B[2:1] = Counter_A[2:1];
Counter_B[0] = !Counter_A[0];