Debugging

The Efinity® software includes a hardware Debugger to probe signals in your FPGA design via the JTAG interface. The Debugger has two perspectives: Profile Editor and Debug. The Profile Editor perspective is where you add debug cores manually. You can also view the settings of a Logic Analyzer core that you created with the Debug Wizard. The Debug perspective is where you perform debugging.

The Debugger includes two debug cores, Virtual I/O (vio) and a Logic Analyzer (la). You use a manual flow and the Profile Editor to configure Virtual I/O cores. You can use a manual flow or the Debug Wizard's automated flow to configure Logic Analyzer cores.

Debugging involves the following general steps:
  1. Create a debug profile with the Virtual I/O and/or Logic Analyzer debugger core(s).
  2. Generate the debug design file and add it to your project.
  3. Compile.
  4. Program the FPGA.
  5. Run the Debugger GUI and observe the values on the probes.
Note: The minimum operating frequency of the debug cores is 2 times the JTAG TCK frequency.