Configuration Status Register
Titanium Topaz FPGAs have a configuration status register. You can use the Efinity Programmer to monitor the values in this register to help debug confugration issues. View the register values in the Advanced Device Configuration Status dialog box, which you open by clicking the button of the same name.
| Name | Description |
|---|---|
| IN_USER | 0: The FPGA is not in user mode. 1: The
FPGA is in user mode. IN_USER waits for
all internal resets and tri-states to be released before it goes
high. Note: This bit is not supported in Ti60ES FPGAs. |
| CDONE | Configuration done, has the same value as the CDONE output
pin. 0: The FPGA is not
configured. 1: Configuation is complete. |
| NSTATUS | Configuration status, has the same value as the active-low NSTATUS
output pin if the NSTATUS pin is not driven by user when the FPGA is in
user mode. 0: Indicates that the FPGA
received a bitstream that was targeted for a different configuration
mode or width, or a CRC error is detected during configuration.
NSTATUS can also go low if there is a mismatch between the bitstream
and the FPGA encryption/authentication keys. 1: During
configuration, indicates that the FPGA is in
configuration mode. |
| CRC32_ERROR_CORE | 0: No CRC errors were detected in the core configuration bits. 1:
One or more CRC errors were detected in the core configuration
bits. |
| RMUPD_ERROR | 0: No errors occurred during remote update. 1: An error occurred
in the golden image during remote update configuration.
|
| CONFIG_END | 0: Configuration is not complete. 1: Configuration completed
(whether successful or not). |
| SYNC_PAT_FOUND | 0: Indicates that the FPGA is not receiving
the expected synchronization pattern at start of the bitstream. Check
for board or power issues. 1: Indicates that the FPGA detected a synchronization pattern at
start of the bitstream., and the clock and data connections to the
FPGA are acceptable. Any configuration
problems are likely digital or logical in nature. After successful
configuration the status will return to 0. |
| SEU_ERROR | 0: No SEU detection errors were found. 1: An SEU detection error
was found when reading back the SEU CRAM. Has the same value as the
SEU detection error status signal to the core fabric. |
| CRC32_ERROR_PERIPH | 0: No CRC errors were detected in the interface configuration bits.
1: One or more CRC errors were detected in the interface
configuration bits. |
| AES256_PASS | For an encrypted bitstream: 0: Decryption failed. The
encryption keys used in to program the fuses may not match the ones used
to encrypt the bitstream 1: The encrypted bitstream was decrypted
successfully. If the bitstream is not encrypted, this
register is always a 1.
Note: This bit is not supported in Ti60ES FPGAs. |
| RSA_PASS | When using RSA authentication: 0: The signature check
failed. The RSA keys used to program the fuses may not match the ones
used to sign the bitstream in the Efinity project.1:
The bitstream signature was verified successfully If RSA
authentication is not used, this register is always a
1. Note: This bit is not supported in Ti60ES FPGAs. |
| AES_ACTIVE | After the FPGA is configured, you can check
this status bit for encryption: 0: AES is disabled in the current
design. 1: AES is enabled in the current
design. |
| RSA_ACTIVE | After the FPGA is configured, you can check
this status bit for authentication: 0: RSA is disabled in the
current device. 1: RSA is enabled in the current
device. |
| USERCODE | Displays the 32-bit hex JTAG USERCODE. |