Output Forward Clock Delay (GPIO clkout)

This example shows how to set constratints for an output forward clock.

Warning: Most designs do not need to use this method. For high-performance designs, use the GPIO registers and follow the instructions in Constraining Synchronous Inputs and Outputs.

Figure 1. Forward Clock Delay (GPIO Output, Register Bypass)

The SDC constraint formulas for the forward clock delay are:

set_output_delay -clock <clock> -reference_pin <clkout interface name> \
   -max <max calculation> <ports>
set_output_delay -clock <clock> -reference_pin <clkout interface name> \
   -min <min calculation> <ports>

Calculate the min and max constraints using the following equations:

<max calculation> = <max board constraint> + GPIO_OUT_max - GPIO_CLK_OUT_max

<min calculation> = <min board constraint> + GPIO_OUT_min - GPIO_CLK_OUT_min

The following example shows how to calculate the delays and set the constraints.

Constraining Output Forward Clock

You want to constrain the o output with respect to clock clk_fwd with a max board constraint of 2 ns and a min board constraint of 2 ns. The non-registered GPIO configuration data from the Interface Designer timing report file is:

Clkout GPIO Configuration:
===========================
 
+---------------+-----------+--------------+----------+----------+--------------------+
| Instance Name | Clock Pin |  Parameter   | Max (ns) | Min (ns) | Reference Pin Name |
+---------------+-----------+--------------+----------+----------+--------------------+
|    clk_fwd    |    clk    | GPIO_CLK_OUT |  2.205   |  1.470   |  clk~CLKOUT~219~1  |
+---------------+-----------+--------------+----------+----------+--------------------+
 
Non-registered HSIO GPIO Configuration:
========================================
 
+---------------+----------+-------------+----------+----------+
| Instance Name | Pin Name |  Parameter  | Max (ns) | Min (ns) |
+---------------+----------+-------------+----------+----------+
|      clk      |   clk    | GPIO_CLK_IN |  0.828   |  0.552   |
|       i       |    i     |   GPIO_IN   |  0.828   |  0.552   |
|       o       |    o     |   GPIO_OUT  |  2.205   |  1.470   |
+---------------+----------+-------------+----------+----------+

The equations are:

<max calculation> = 2 + 2.205 - 2.205 = 2

<min calculation> = 2 + 1.470 - 1.470 = 2

The resulting constraints are:

set_output_delay -clock clk -reference_pin clk~CLKOUT~219~1 -max 2 [get_ports {o}]
set_output_delay -clock clk -reference_pin clk~CLKOUT~219~1 -min 2 [get_ports {o}]