syn_keep

This attribute applies to signals or wires. It is similar to syn_preserve except it keeps more than just the signal itself. When it is set to true, yes, or 1, the synthesis tool keeps the driver and the loads of the signal through optimization (synthesis does not minimize or remove them).

Verilog HDL:

(* syn_keep = "true" *) wire x;

VHDL:

attribute syn_keep: boolean;
attribute syn_keep of x : signal is true;

Note: A signal with syn_keep usually has it’s name preserved through synthesis flow. However, if the signal is connected directly to a top-level port, the name in the map.v netlist may be changed to that of the top-level port name.