syn_use_dsp

You use this attribute on multiplier output signals.
  • When set to true, yes, or 1, the synthesis tool implements the multiply function using hard multipliers (that is, the EFX_MULT primitive).
  • When set to false, no, or 0, the synthesis tool generates adders and logic for the multiply function.
In Titanium FPGAs, applying this attribute to the output of an adder that is driven on one side by a multiplier tells synthesis to try to pack the adder into the DSP Block by:
  • Using an extra DSP Block to feed the other operand through the cascin/cascout path.
  • If possible, pack a feedback loop through the N-SEL path so that the multiply-accumulate is implemented in a single DSP Block.
Verilog HDL: 
(* syn_use_dsp = "yes" *) signed [27:0] x;
VHDL: 
attribute syn_use_dsp: boolean;
attribute syn_use_dsp of x : signal is true;