translate_on, translate_off

You use these directives to tell the synthesis tool to ignore the code within them. You should use these together; a translate_off should have a corresponding translate_on.

For example, the FPGA's flipflop powers up to a 0 value. For simulation, you need to initialize the registers to 0 for the simulation to match this behavior. Using this directive allows the synthesis tool to demonstrate the FPGA's default behavior.

Verilog HDL:

module in_shifter #(parameter N=2)
(
input data,
input clk,
output reg [N-1:0] out
);
  
   reg [N-1:0]      shift_reg;
 
   // synthesis translate_off
   initial begin
       shift_reg = 0;
       out = 0;
   end
   // synthesis translate_on
  
   always @(posedge clk)
     begin
         shift_reg <= {shift_reg[N-2:0],data};
         out <= shift_reg;
     end
endmodule // in_shifter