Generate Statements (11.8)

In VHDL 2008 you can use case statements in generate statements, and else/elsif in if statements.

generate_test: case sel generate -- sel must be a constant
                  when "00" =>
                     comp1: entity work.test1(behave)
                            port map(B(13),A(13),C(27));
                  when "01" =>
                     comp1: entity work.test2(behave)
                            port map(B(13),A(13),C(27));
                  when others => 
end generate;