Simulate with the iVerilog Simulator

By default, the Efinity® software calls the iVerilog simulator. Use the --flow rtlsim|mapsim flag. This free simulator has limitiations: it cannot decrypt code (such as IP from the IP Manager), and it does not support SystemVerilog.

Note: You can download the free Icarus Verilog (iVerilog) simulator from iverilog.icarus.com.
Note: Windows: You may need to add the path to iVerilog ($iVerilog_folder$\bin\) to your System Variables path for the software to launch correctly.

For example, the commands to simulate are:

Simulate with iVerilog

Linux:
efx_run.py <project name>.xml --flow rtlsim     // Behavioral simulation
efx_run.py <project name>.xml --flow map        // Synthesize the design
efx_run.py <project name>.xml --flow mapsim     // Post-synthesis simulation
Windows:
efx_run.bat <project name>.xml --flow rtlsim     // Behavioral simulation
efx_run.bat <project name>.xml --flow map        // Synthesize the design
efx_run.bat <project name>.xml --flow mapsim     // Post-synthesis simulation
The simulator responds with
  • PASS if the simulation is successful.
  • a Python exception warning if the simulation is unsuccessful.

The software saves simulation results (<flow>.rtl.simlog and <flow>.map.simlog) and error messages (<flow>.log) in your project's outflow directory.