syn_ramdecomp

This attribute applies to a RAM or ROM signal and controls how synthesis decomposes the RAM or ROM.

When this attribute is not set, synthesis always chooses data-width decomposition for better performance.
When set to area. synthesis decomposes the RAM or ROM for minimum area (least number of RAM block primitives), but it favors data-width decomposition.
When set to power, synthesis decomposes the RAM or ROM for minimum area, but it favors address decomposition.

Verilog HDL:

(* syn_ramdecomp = "area" *) reg [DWIDTH-1:0]         mem [DEPTH-1:0];
(* syn_ramdecomp = "power" *) reg [DWIDTH-1:0]        mem [DEPTH-1:0];

VHDL:

attribute syn_ramdecomp: string;
attribute syn_ramdecomp of mem : signal is "power";

Note: You can use the Block RAM Resource Estimator to explore the number of blocks synthesis will use for various settings. Refer to Estimating Block RAM Resources for details.