Block Types and Device Settings
The following tables list the block types and device setings the Interface Designer Python API supports, organized by Efinity® release.
| Block Description | Block Name | Trion | Titanium | Topaz | |||
|---|---|---|---|---|---|---|---|
| 2025.1 | 2025.2 | 2025.1 | 2025.2 | 2025.1 | 2025.2 | ||
| Single GPIO. | GPIO |  |
|
|
|
|
|
| GPIO bus. | GPIO_BUS | |
|
|
|
|
|
| JTAG User Tap block. | JTAG | |
|
|
|
|
|
| LVDS block. | LVDS_RX LVDS_TX |
|
|
|
|
|
|
|
LVDS_BIDIR
|
– | – | |
|
|
|
|
| Oscillator block. | OSC | |
|
|
|
|
|
| Simple PLL block (PLL V1). Advanced PLL block (PLL
V2). |
PLL | |
|
– | – | – | – |
| PLL block (PLL V3). | PLL | – | – | |
|
|
|
| Fractional PLL block (FPLL V1). | PLL | – | – | |
|
|
|
| PLL SSC block. | PLL_SSC | – | – | |
|
|
|
| MIPI RX or TX block. | MIPI_TX MIPI_RX |
|
|
– | – | – | – |
| MIPI TX or RX Lane block. | MIPI_RX_LANE MIPI_TX_LANE |
– | – | |
|
|
|
| MIPI D-PHY TX or RX block. | MIPI_DPHY_TX MIPI_DPHY_RX |
– | – | |
|
|
|
| DDR DRAM block. | DDR | |
|
|
|
|
|
| HyperRAM block. | HYPERRAM | – | – | |
|
– | |
| SPI Flash block. | SPI_FLASH | |
|
|
|
|
|
| PCIe transceiver quad. | QUAD_PCIE | – | – | |
|
– | |
| PMA Direct lane. | PMA_DIRECT | |
|
– | |
||
| Ethernet XGMII lane. | 10GBASE_KR | – | – | |
|
– | |
| Ethernet SGMII lane. | SGMII | – | – | – | |
– | |
| Setting | Setting Name | Trion | Titanium | Topaz | |||
|---|---|---|---|---|---|---|---|
| 2025.1 | 2025.2 | 2025.1 | 2025.2 | 2025.1 | 2025.2 | ||
| I/O Banks | IOBANK | |
|
|
|
|
|
| Remote Update | RU | |
|
|
|
|
|
| Enable User Status Control | RU1 | – | – | – | |
|
|
| SEU | SEU | – | – | |
|
|
|
| Clock Mux | CLKMUX | – | – | |
|
|
|
| External Flash Controller | EXT_FLASH | – | – | |
|
|
|
1 This setting is combined with the remote update settings and
support.