HyperRAM Property Reference

All of these HyperRAM block properties are applicable to Titanium FPGAs in F100S3F2 packages only.

Table 1. HyperRAM Properties
API Name	GUI Name	Values
CK_N_HI_PIN	Differential Clock Pin Name (N HI)	Pin name
CK_N_LO_PIN	Differential Clock Pin Name (N LO)	Pin name
CK_P_HI_PIN	Differential Clock Pin Name (P HI)	Pin name
CK_P_LO_PIN	Differential Clock Pin Name (P LO)	Pin name
CLK_PIN	HyperRAM Controller Clock Pin Name	Pin name
CLK90_PIN	90 Degree Phase-Shifted Clock Pin Name	Pin name
CLKCAL_PIN	Calibration Clock Pin Name	Pin name
CS_N_PIN	Active-Low HyperRAM Chip Select Pin Name	Pin name
DQ_IN_HI_PIN	DQ Input [15:0] Bus Name (HI)	Pin name
DQ_IN_LO_PIN	DQ Input [15:0] Bus Name (LO)	Pin name
DQ_OE_PIN	DQ Output Enable [15:0] Bus Name	Pin name
DQ_OUT_HI_PIN	DQ Output [15:0] Bus Name (HI)	Pin name
DQ_OUT_LO_PIN	DQ Output [15:0] Bus Name (LO)	Pin name
NAME	Instance Name	Instance Name
RESOURCE	HyperRAM Resource	Pin name
RST_N_PIN	Active-Low HyperRAM Reset Pin Name	Pin name
RWDS_IN_HI_PIN	Read/Write Data Strobe Input [1:0] Bus Name (HI)	Pin name
RWDS_IN_LO_PIN	Read/Write Data Strobe Input [1:0] Bus Name (LO)	Pin name
RWDS_OE_PIN	Read/Write Data Strobe Output Enable [1:0] Bus Name	Pin name
RWDS_OUT_HI_PIN	Read/Write Data Strobe Output [1:0] Bus Name (HI)	Pin name
RWDS_OUT_LO_PIN	Read/Write Data Strobe Output [1:0] Bus Name (LO)	Pin name
RST_DRIVE_STRENGTH	Active-Low HyperRAM Reset Drive Strength (mA)	4, 8, 12, 16
CS_DRIVE_STRENGTH	Active-Low HyperRAM Chip Select Drive Strength (mA)	4, 8, 12, 16
CK_DRIVE_STRENGTH	HyperRAM Clock Drive Strength (mA)	4, 8, 12, 16
RWDS_DRIVE_STRENGTH	Read/Write Data Strobe Drive Strength (mA)	4, 8, 12, 16
DQ_DRIVE_STRENGTH	DQ [15:0] Bus Drive Strength (mA)	4, 8, 12, 16