<project>.map.core.v
| In GUI | |
| In file system | <project>/outflow |
| Created by | Efinity software during the synthesis step. |
| Design source? | No |
The Efinity software creates this file during the synthesis step. This file has the post-mapping core netlist that you use for simulation in the unified design flow. This file is only generated in the unified design flow and contains only the core logic.