Ethernet XGMII Property Reference

These Ethernet XGMII block properties are only applicable to Titanium FPGAs with transceivers. Refer to the data sheet for which packages have transceivers.

Table 1. Base Properties

API Name	GUI Name	Values
NAME	Instance Name	Instance name
RESOURCE	10GE Resource	Resource

Table 2. Control Register Properties

API Name	GUI Name	Values
10G_PCS_L_NID__CONTROL_REGISTER__USX_SPEED	Speed	5GHz, 10GHz
SS_10GBE_L_NID_ENABLE_FEC	Enable Forward Error Correction (FEC)	0, 1
10G_PCS_L_NID__CONTROL_REGISTER__TX_POL_INVERT	Invert TX Polarity	0, 1
10G_PCS_L_NID__CONTROL_REGISTER__RX_POL_INVERT	Invert RX Polarity	0, 1
10G_PCS_L_NID__CONTROL_REGISTER__USX_AN_ENABLE	Enable Auto Negotiation (AN) Clause 37	0, 1
10G_PCS_L_NID__CONTROL_REGISTER__USX_AN_OS_CODE	USXGMII AN Ordered set code	0x0 - 0xff

Table 3. Clock and Reset Properties

API Name	GUI Name	Values
LN_10GBE_CONN_TYPE	Interface Clock Input Connection Type	rclk, gclk
10GBE_CLK_PIN	Interface Clock Input Pin Name	Pin name
PCS_RST_N_RX_PIN	PCS Receive Reset Pin Name	Pin name
PCS_RST_N_TX_PIN	PCS Transmit Reset Pin Name	Pin name
PHY_RESET_N_PIN	PHY Lane Reset Pin Name	Pin name

Table 4. Control Properties

API Name	GUI Name	Values
ETH_EEE_ALERT_EN_PIN	Ethernet EEE Alert Enable Pin Name	Pin name
PMA_TX_ELEC_IDLE_PIN	PMA Transmit Electrical Idle Pin Name	Pin name
SW_10GBE_L_NID_KR_ENABLE	Enable KR Base	0, 1

Table 5. KR Training Properties

API Name	GUI Name	Values
KR_FRAME_LOCK_PIN	10G-KR Frame Locked Pin Name	Pin name
KR_LOCAL_RX_TRAINED_PIN	10G-KR Receiver Trained Pin Name	Pin name
KR_RESTART_TRAINING_PIN	Restart Link Training Pin Name	Pin name
KR_SIGNAL_DETECT_PIN	10G-KR Training Signal Detect Pin Name	Pin name
KR_TRAINING_PIN	Link Training Initiated Indication Pin Name	Pin name
KR_TRAINING_ENABLE_PIN	Link Training Enable Pin Name	Pin name
KR_TRAINING_FAILURE_PIN	Link Training Failure Pin Name	Pin name

Table 6. Error and Status Properties

API Name	GUI Name	Values
BLOCK_LOCK_PIN	Block Lock Status Pin Name	Pin name
HI_BER_PIN	High Bit Error Ratio Status Pin Name	Pin name
IRQ_PIN	Interrupt Pin Name	Pin name
PCS_STATUS_PIN	PCS Ready Status Pin Name	Pin name
PHY_INTERRUPT_PIN	PHY Interrupt Pin Name	Pin name

Table 7. Power Up Properties

API Name	GUI Name	Values
PMA_RX_SIGNAL_DETECT_PIN	PMA Receiver Signal Detect Pin Name	Pin name
PMA_XCVR_PLLCLK_EN_PIN	Link PLL Clock Enable Pin Name	Pin name
PMA_XCVR_PLLCLK_EN_ACK_PIN	Link PLL Clock Enable Acknowledge Pin Name	Pin name
PMA_XCVR_POWER_STATE_ACK_PIN	Link Power State Acknowledge [3:0] Bus Name	Bus name
PMA_XCVR_POWER_STATE_REQ_PIN	Link Power State Request [3:0] Bus Name	Bus name

Table 8. XGMII Properties

API Name	GUI Name	Values
RXC_PIN	Receive Control [7:0] Bus Name	Bus name
RXD_PIN	Receive Data [63:0] Bus Name	Bus name
TXC_PIN	Transmit Control [7:0] Bus Name	Bus name
TXD_PIN	Transmit Data [63:0] Bus Name	Bus name

Table 9. Common Properties: APB

API Name	GUI Name	Values
USER_APB_CLK_PIN	APB Clock Pin Name	Pin name
USER_APB_CLK_INVERT_EN	Invert APB Clock Pin	1, 0
USER_APB_PADDR_PIN	APB Address [23:0] Bus Name	Bus name
USER_APB_PENABLE_PIN	APB Enable Pin Name	Pin name
USER_APB_PRDATA_PIN	APB Read Data [31:0] Bus Name	Bus name
USER_APB_PREADY_PIN	APB Ready Pin Name	Pin name
USER_APB_PSEL_PIN	APB Select Pin Name	Pin name
USER_APB_PWDATA_PIN	APB Write Data [31:0] Bus Name	Bus name
USER_APB_PWRITE_PIN	APB Write Pin Name	Pin name

Table 10. Common Properties: Clock and Reset

API Name	GUI Name	Values
PHY_RESET_EN	Enable PHY Quad Reset Pin	0, 1
PHY_CMN_RESET_N_PIN	PHY Quad Reset Pin Name	Pin name

Table 11. Common Properties: Error and Status

API Name	GUI Name	Values
PMA_CMN_READY_PIN	PHY Ready Pin Name	Pin name

Table 12. Common Properties: Configuration

API Name	GUI Name	Values
COMMON_INST_NAME	Common Instance Name	Read only1
PLL_LC_CONN	Common PLL Connection	Refclk 0, Refclk 0 and 1
SS_REFCLK_FREQ	Reference Clock 0 Frequency (MHz)	156.25
PIPE_CONFIG_CMN__CONFIG_REG_2__PMA_CMN_REFCLK_SEL	Reference Clock 0 Source	External
PIPE_CONFIG_CMN__CONFIG_REG_2__PMA_CMN_REFCLK_TERMEN	Enable 50 Ω to ground on-die termination for REFCLK 0	1, 0
SS_REFCLK_FREQ_2	Reference Clock 1 Frequency (MHz)	156.25
PIPE_CONFIG_CMN__CONFIG_REG_2__PMA_CMN_REFCLK1_SEL	Reference Clock 1 Source	External
PIPE_CONFIG_CMN__CONFIG_REG_2__PMA_CMN_REFCLK1_TERMEN	Enable 50 Ω to ground on-die termination for Refclk 1
SS_REFCLK_ONBOARD_OSC	Reference clock from on-board crystal	0, 1
REFCLK_SEL	Reference Clock Select	Refclk 0, Refclk 1
SS_REFCLK_FREQ	Reference Clock 0 Frequency (MHz)	19.19:156.28
PIPE_CONFIG_CMN__CONFIG_REG_2__​PMA_CMN_REFCLK_SEL	Reference Clock 0 Source	External, Internal
REF_CLK_INTERNAL_SRC	Internal Source	Core, PLL
PMA_CMN_REFCLK_CORE_PIN	PMA Core Reference Clock Pin Name
SS_REFCLK_FREQ_2	Reference Clock 1 Frequency (MHz)	19.19:156.28
PIPE_CONFIG_CMN__CONFIG_REG_2__​PMA_CMN_REFCLK1_SEL	Reference Clock 1 Source	External, Internal
REF_CLK1_INTERNAL_SRC	Internal Source	Core, PLL
PMA_CMN_REFCLK1_CORE_PIN	PMA Core Reference Clock Pin Name