Example: Clock-to-Clock Path with Control

The following figure shows a use case in which a specific clock-to-clock path in a design can have special control logic. The path from FF1 to FF2 can have a different timing exception compared to other clock-to-clock paths in the design. You define these timing exceptions with set_false_path, set_max_delay, set_min_delay, or set_multicycle_path SDC commands.