Logic Analyzer Debug Core

You use the Logic Analyzer core (la) to monitor the signals in your design. You can capture connected wire or register values over a specified time period or after a specific number of times the trigger condition occurs (the default is 1). During runtime, the core samples the signals and saves the data into the FPGA's block RAM. You can specify the number of probes, the buffer depth, and the width for each probe input. Additionally, you can set global AND, OR, NAND, and NOR trigger conditions as well as segment triggers.

You add a Logic Analyzer core manually or using the Debug Wizard, compile your design, and program the FPGA. Then, you use the Debugger to set trigger events. When a trigger occurs, the core fills the sample buffer and loads the results into the Debugger's Debug Perspective. You can view this data using the GTK waveform viewer.

Note: Learn how to use the Debug Wizard >

Functional Description

The Logic Analyzer core has an interface to the JTAG User Tap block, a clock, user-specified probes and trigger-related signals.

Figure 1. Logic Analyzer Core Block Diagram
Table 1. Logic Analyzer Core Ports
Port Direction Description
<core>_clk Input Clock for triggers. At a minimum, this clock should run at twice the speed of the JTAG clock. The Debugger uses a JTAG clock of 3 MHz, so this clock should be 6 MHz or higher.
<core>_<probe name>[n:0] Input Probes you add in the Profile Editor. You can add a maximum on 64 probes; the maximum probe width is 256 bits.
<core>_trig_in Input Input trigger. You can connect this port to another Logic Analyzer core to build a cascading chain of triggers. Alternatively, you can connect it to an external source such as an oscilloscope.
<core>_trig_in_ack Output Input trigger acknowledge.
<core>_trig_out Output Output trigger. This trigger can be generated from an external trigger condition or from the <core>_trig_in port of another Logic Analyzer core.
<core>_trig_out_ack Input Output trigger acknowledge.
bscan_CAPTURE Input Capture output from the TAP controller.
bscan_DRCK Input Gated TCK output.
bscan_RESET Input Reset output for the TAP controller.
bscan_RUNTEST Input Output asserted when the TAP controller is in the Run Test / Idle state.
bscan_SEL Input USER instruction active output.
bscan_SHIFT Input SHIFT output from TAP controller.
bscan_TCK Input JTAG test clock input (TCK).
bscan_TDI Input JTAG test data input (TDI).
bscan_TMS Input JTAG test mode select input (TMS).
bscan_UPDATE Input UPDATE output from TAP controller.
bscan_TDO Output JTAG test data output (TDO).

Adding a Logic Analyzer Core Manually

  1. Open the Debugger.
  2. Choose Perspectives > Profile Editor.
  3. Input a debug profile name into the Profile name field.
  4. Choose Add Debug Core > Logic Analyzer.
  5. Specify the core name.
  6. Select the data depth. This settings lets you control how much data is saved for the probes. The more data you save, the more on-chip memory is used.
  7. Turn on Trigger In Port and/or Trigger Out Port to enable those signals.
  8. Turn on Capture Control if you want to change the capture mode in the Capture Setup tab during debugging (see Debug Perspective for details). If you turn this option on, the Logic Analyzer uses more FPGA resources.
  9. Add probes (outputs from your design to the JTAG interface).
    1. Choose a width and specify the signal to which you want to connect the probe in your design.
    2. Choose Data and Trigger (default) to save data and can trigger when to capture.
      Choose Data Only to save data.
      Choose Trigger Only to trigger when to capture data. Tigger only signals do not display in the resulting waveform.
  10. Click Generate Core RTL. The Efinity® software saves the debug profile in your project directory as <profile name>.json. The software also creates a debug template (<profile name>_TEMPLATE.v), which includes the module for the debug profile you created and <profile name>_top.v, which is the RTL logic for the debug core.
  11. Add the <profile name>_top.v file to your project.
    Tip: In the Project pane, right-click Design and choose Add to open a dialog box to find the file and add it.
  12. Add a JTAG User Tap block in the Interface Designer. You can choose either JTAG resource.
    Note: the debug template uses the default signal names prefixed with jtag_inst1. If you use a different name, then you should also change it in the module instantiation.
  13. Add the debug logic into your design using these steps:
    1. Add all of the JTAG input and output pins to the project's top module. Refer to the JTAG User TAP block pin names in the Interfaces Design to get the pin list.
    2. Instantiate the debug core in the project's top module. You can copy the example code from the generated <profile name>_TEMPLATE.v or <profile name>_TEMPLATE.vhd file in the project folder.
    3. Connect the nets that you want to monitor and drive the FPGA signals. You need to map the net (input, output, wire, register, and/or signal) to the port of the instantiated debug core (edb_top_inst).
  14. Compile the design.

When compilation completes, you can launch the Debugger to perform debugging.

Note: For complex designs with multiple levels of hierarchy, it can be time-consuming to implement the Logic Analyzer core manually. Instead, use the Debug Wizard. Learn about the Debug Wizard >